US4345328A
Expired / Lapsed
US
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ECC Check bit generation using through checking parity bits
Assignee: Samsung Electronics Co Ltd
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Filing: 1980-06-30
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Granted: 1982-08-17
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Expires: 2000-06-30
Abstract
Abstract Apparatus for and method of providing single bit error correction and double bit error detection using through checking parity bits. A coding scheme is implemented which uses through checking parity bits appended to each byte as check bits. The remaining check bits are generated such that the combination of through checking parity bits and remaining check bits together provide single bit error correction and double bit error detection.
Inventors
- 👤 Gary D. White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:04
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
200 words
A memory system which provides single bit error correction/double bit error detection and through checking comprising: an input data register capable of temporarily storing and outputting a data quantity having n data bit positions and x through checking parity bits; a memory having a plurality of addressable locations input from said input data register wherein each of said plurality of addressable locations is capable of storing said data quantity and said x through checking parity bits and y coded check bits; means input by said input data register and outputting to said memory for generating said y coded check bits such that the combination of said y coded check bits and said x through checking parity bits is sufficient to enable correction of a single bit error in said data quantity and to enable detection of a double bit error in said data quantity, and such that n>2y; an output data register capable of temporarily storing said data quantity and said x through checking parity bits; and means input by said memory and outputting to said output data register for performing single bit error correction upon said data quantity received from said memory before transfer to said output data register.
Claim 2
Dependent Claim
200 words
A memory system which provides single bit error correction/double bit error detection and through checking comprising: an input data register capable of temporarily storing and outputting a data quantity having n data bit positions and x through checking parity bits; a memory having a plurality of addressable locations input from said input data register wherein each of said plurality of addressable locations is capable of storing said data quantity and said x through checking parity bits and y coded check bits; means input by said input data register and outputting to said memory for generating said y coded check bits such that the combination of said y coded check bits and said x through checking parity bits is sufficient to enable correction of a single bit error in said data quantity and to enable detection of a double bit error in said data quantity, and such that n>2y; an output data register capable of temporarily storing said data quantity and said x through checking parity bits; and means input by said memory and outputting to said output data register for performing single bit error correction upon said data quantity received from said memory before transfer to said output data register.
Claim 3
Dependent Claim
15 words
A memory system according to claim 1 further defined such that: n=36; x=4; and y=5.
Claim 4
Dependent Claim
41 words
A memory system according to claim 1 or 2 wherein said data quantity has a plurality of bytes and each of said x through checking parity bits is a parity bit for a different corresponding one of said plurality of bytes.
Claim 5
Dependent Claim
190 words
In a memory system receiving, storing, and outputting quantities consisting of both n data bits and x through checking parity bits, a method of single bit error correction on said stored quantities comprising: receiving as input said quantities consisting of both n data bits and x through checking parity bits and storing said through-checked quantity; generating in consideration of said n data bits an error correction code of y bits wheren n>2y, meaning that y bits are of themselves insufficient in number of single bit error correction of said n data bits; storing said y bits of error correction code along with said through-checked quantity of n data bits and x through checking parity bits; retrieving said stored quantities of n data bits and x through checking parity bits and y error correction bits; generating z miscompare bits called syndromes based on said n data bits and said y error correction bits; utilizing said z syndrome bits and said x through checking parity bits to effect single error correction within said n data bits; and outputting said single error corrected in data bits and said x through checking parity bits.
Claim 6
Dependent Claim
190 words
In a memory system receiving, storing, and outputting quantities consisting of both n data bits and x through checking parity bits, a method of single bit error correction on said stored quantities comprising: receiving as input said quantities consisting of both n data bits and x through checking parity bits and storing said through-checked quantity; generating in consideration of said n data bits an error correction code of y bits wheren n>2y, meaning that y bits are of themselves insufficient in number of single bit error correction of said n data bits; storing said y bits of error correction code along with said through-checked quantity of n data bits and x through checking parity bits; retrieving said stored quantities of n data bits and x through checking parity bits and y error correction bits; generating z miscompare bits called syndromes based on said n data bits and said y error correction bits; utilizing said z syndrome bits and said x through checking parity bits to effect single error correction within said n data bits; and outputting said single error corrected in data bits and said x through checking parity bits.
Claim 7
Dependent Claim
46 words
The single bit error correction method of claim 4 adapted for single and double bit error detection and further comprising: utilizing said z syndrome bits to detect single bit errors and to detect double bit errors; and outputting said detection of single and double bit errors.
Claim 8
Dependent Claim
12 words
A method according to claim 4 wherein n=36, x=4, y=5, and z=9.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-16 | 1986-02-15 | 1986-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-16 | 1990-02-15 | 1990-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-16 | 1994-02-15 | 1994-08-17 | $7700.00 | Window Closed / Lapsed |