Patent US5098638A successfully refreshed from Google Patents.
US5098638A
Expired / Lapsed
US
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Method of manufacturing a semiconductor device
Assignee: Panasonic Holdings Corp
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Filing: 1990-04-25
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Granted: 1992-03-24
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Expires: 2010-04-25
Abstract
Abstract A method of manufacturing a semiconductor device forms an intrinsic base layer by doping an impurity in the emitter polysilicon electrode into the intrinsic base region of the surface of a semiconductor substrate by heat treatment through the emitter lead-out part hole self-aligned to the base lead-out electrode. Thus, beneath the insulation film of the substrate surface between the base lead-out part hole and emitter lead-out part hole, the outer marginal part of the intrinsic base layer and the inner marginal part of the extrinsic base layer overlap uniformly. Still more, since the diffusion of the impurity by heat treatment is very fast in the polysilicon emitter electrode as compared with that in the silicon substrate, an extremely shallow intrinsic base layer may be formed.
Inventors
- 👤 Shigeki Sawada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:43
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D10/441; H10D62/00; H10D62/10; H10D62/13; H10D62/137; H10D62/138; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/123; Y10S148/124
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
296 words
A method of manufacturing a semiconductor device comprising the steps of: forming a buried collector layer on a semiconductor substrate; growing an epitaxial layer having a thickness of 1.5 μm or less on said buried collector layer; selectively forming a first insulation film in said epitaxial layer thereby defining a portion of said epitaxial layer surrounded by said first insulation film as an intrinsic base region; forming a first semiconductor film on said first insulation film and said intrinsic base region; removing a portion of said first semiconductor film so as to expose a surface of a center region of said intrinsic base region; forming a second insulation film at least on an exposed surface of said intrinsic base region and a sidewall of said first semiconductor film; forming an extrinsic base layer in a peripheral area of said intrinsic base region by diffusing a first impurity contained in said first semiconductor film into said peripheral area of said intrinsic base region through a gap between a sidewall of said first insulation film and the sidewall of said first semiconductor film; forming a second insulation film in a recess surrounded by said second insulation film; forming an emitter lead-out part hole by removing a center portion of said second semiconductor film and said second insulation film disposed on said intrinsic base region; forming a third semiconductor film in said emitter lead-out part hole; forming an intrinsic base layer in said intrinsic base region by diffusing a second impurity contained in said third semiconductor film thereby overlapping an outer marginal area of said intrinsic base layer and an inner marginal area of said extrinsic base layer, and forming an emitter layer in said intrinsic base layer by diffusing a third impurity contained in said third semiconductor film.
Claim 2
Independent Claim
296 words
A method of manufacturing a semiconductor device comprising the steps of: forming a buried collector layer on a semiconductor substrate; growing an epitaxial layer having a thickness of 1.5 μm or less on said buried collector layer; selectively forming a first insulation film in said epitaxial layer thereby defining a portion of said epitaxial layer surrounded by said first insulation film as an intrinsic base region; forming a first semiconductor film on said first insulation film and said intrinsic base region; removing a portion of said first semiconductor film so as to expose a surface of a center region of said intrinsic base region; forming a second insulation film at least on an exposed surface of said intrinsic base region and a sidewall of said first semiconductor film; forming an extrinsic base layer in a peripheral area of said intrinsic base region by diffusing a first impurity contained in said first semiconductor film into said peripheral area of said intrinsic base region through a gap between a sidewall of said first insulation film and the sidewall of said first semiconductor film; forming a second insulation film in a recess surrounded by said second insulation film; forming an emitter lead-out part hole by removing a center portion of said second semiconductor film and said second insulation film disposed on said intrinsic base region; forming a third semiconductor film in said emitter lead-out part hole; forming an intrinsic base layer in said intrinsic base region by diffusing a second impurity contained in said third semiconductor film thereby overlapping an outer marginal area of said intrinsic base layer and an inner marginal area of said extrinsic base layer, and forming an emitter layer in said intrinsic base layer by diffusing a third impurity contained in said third semiconductor film.
Claim 3
Independent Claim
322 words
A method of manufacturing a semiconductor device comprising the steps of: forming a buried collector layer on a semiconductor substrate; growing an epitaxial layer with an arsenic concentration of 5×10 15 to 3×10 16 cm -3 on said buried collector layer by a CVD method at a temperature of 1100° C. or less and a low pressure on the order of 100 Torr.; selectively forming a first insulation film in said epitaxial layer thereby defining a portion of said epitaxial layer surrounded by said first insulation film as an intrinsic base region; forming a first semiconductor film on said first insulation film and said intrinsic base region; removing a portion of said first semiconductor film so as to expose a surface of a center region of said intrinsic base region; forming a second insulation film at least on an exposed surface of said intrinsic base region and a sidewall of said first semiconductor film; forming an extrinsic base layer in a peripheral area of said intrinsic base region by diffusing a first impurity contained in said first semiconductor film into said peripheral area of said intrinsic base region through a gap between a sidewall of said first insulation film and the sidewall of said first semiconductor film; forming a second insulation film in a recess surrounded by said second insulation film; forming an emitter lead-out part hole by removing a center portion of said second semiconductor film and said second insulation film disposed on said intrinsic base region; forming a third semiconductor film in said emitter lead-out part hole; forming an intrinsic base layer in said intrinsic base region by diffusing a second impurity contained in said third semiconductor film thereby overlapping an outer marginal area of said intrinsic base layer and an inner marginal area of said extrinsic base layer, and forming an emitter layer in said intrinsic base layer by diffusing a third impurity contained in said third semiconductor film.
Claim 4
Independent Claim
322 words
A method of manufacturing a semiconductor device comprising the steps of: forming a buried collector layer on a semiconductor substrate; growing an epitaxial layer with an arsenic concentration of 5×10 15 to 3×10 16 cm -3 on said buried collector layer by a CVD method at a temperature of 1100° C. or less and a low pressure on the order of 100 Torr.; selectively forming a first insulation film in said epitaxial layer thereby defining a portion of said epitaxial layer surrounded by said first insulation film as an intrinsic base region; forming a first semiconductor film on said first insulation film and said intrinsic base region; removing a portion of said first semiconductor film so as to expose a surface of a center region of said intrinsic base region; forming a second insulation film at least on an exposed surface of said intrinsic base region and a sidewall of said first semiconductor film; forming an extrinsic base layer in a peripheral area of said intrinsic base region by diffusing a first impurity contained in said first semiconductor film into said peripheral area of said intrinsic base region through a gap between a sidewall of said first insulation film and the sidewall of said first semiconductor film; forming a second insulation film in a recess surrounded by said second insulation film; forming an emitter lead-out part hole by removing a center portion of said second semiconductor film and said second insulation film disposed on said intrinsic base region; forming a third semiconductor film in said emitter lead-out part hole; forming an intrinsic base layer in said intrinsic base region by diffusing a second impurity contained in said third semiconductor film thereby overlapping an outer marginal area of said intrinsic base layer and an inner marginal area of said extrinsic base layer, and forming an emitter layer in said intrinsic base layer by diffusing a third impurity contained in said third semiconductor film.
Claim 5
Independent Claim
330 words
A method of manufacturing a semiconductor device comprising the steps of: forming a buried collector layer on a semiconductor substrate; growing an epitaxial layer with an arsenic concentration of 5×10 15 to 3×10 16 cm -3 and a thickness of 1.5 μm or less on said buried collector layer by a CVD method at a temperature of 1100° C. or less and a low pressure on the order of 100 Torr.; selectively forming a first insulation film in said epitaxial layer thereby defining a portion of said epitaxial layer surrounded by said fist insulation film as an intrinsic base region; forming a first semiconductor film on said first insulation film and said intrinsic base region; removing a portion of said first semiconductor film so as to expose a surface of a center region of said intrinsic base region; forming a second insulation film at least on an exposed surface of said intrinsic base region and a sidewall of said first semiconductor film; forming an extrinsic base layer in a peripheral area of said intrinsic base region by diffusing a first impurity contained in said first semiconductor film into said peripheral area of said intrinsic base region through a gap between a sidewall of said first insulation film and the sidewall of said first semiconductor film; forming a second insulation film in a recess surrounded by said second insulation film; forming an emitter lead-out part hole by removing a center portion of said second semiconductor film and said second insulation film disposed on said intrinsic base region; forming a third semiconductor film in said emitter lead-out part hole; forming an intrinsic base layer in said intrinsic base region by diffusing a second impurity contained in said third semiconductor film thereby overlapping an outer marginal area of said intrinsic base layer and an inner marginal area of said extrinsic base layer, and forming an emitter layer in said intrinsic base layer by diffusing a third impurity contained in said third semiconductor film.
Claim 6
Independent Claim
330 words
A method of manufacturing a semiconductor device comprising the steps of: forming a buried collector layer on a semiconductor substrate; growing an epitaxial layer with an arsenic concentration of 5×10 15 to 3×10 16 cm -3 and a thickness of 1.5 μm or less on said buried collector layer by a CVD method at a temperature of 1100° C. or less and a low pressure on the order of 100 Torr.; selectively forming a first insulation film in said epitaxial layer thereby defining a portion of said epitaxial layer surrounded by said fist insulation film as an intrinsic base region; forming a first semiconductor film on said first insulation film and said intrinsic base region; removing a portion of said first semiconductor film so as to expose a surface of a center region of said intrinsic base region; forming a second insulation film at least on an exposed surface of said intrinsic base region and a sidewall of said first semiconductor film; forming an extrinsic base layer in a peripheral area of said intrinsic base region by diffusing a first impurity contained in said first semiconductor film into said peripheral area of said intrinsic base region through a gap between a sidewall of said first insulation film and the sidewall of said first semiconductor film; forming a second insulation film in a recess surrounded by said second insulation film; forming an emitter lead-out part hole by removing a center portion of said second semiconductor film and said second insulation film disposed on said intrinsic base region; forming a third semiconductor film in said emitter lead-out part hole; forming an intrinsic base layer in said intrinsic base region by diffusing a second impurity contained in said third semiconductor film thereby overlapping an outer marginal area of said intrinsic base layer and an inner marginal area of said extrinsic base layer, and forming an emitter layer in said intrinsic base layer by diffusing a third impurity contained in said third semiconductor film.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |