Fabrication process for a shallow emitter, narrow intrinsic base transistor

Claim 1

A process for forming a transistor having a shallow emitter region and a narrow intrinsic base region and an extrinsic base region including the successive steps of: depositing a layer of polycrystalline silicon on a semiconductor substrate provided with a subcollector, an epitaxial layer, isolated regions, and oxide surface with holes open in the oxide surface for the extrinsic base, intrinsic base and emitter region, thermally oxidizing the surface of the polycrystalline silicon layer, implanting a base impurity into the polycrystalline silicon layer, removing the surface oxide layer and the polycrystalline silicon layer from a subcollector reach-through area, depositing a silicon nitride layer, over the structure, depositing a silicon dioxide layer, over the structure, opening the silicon dioxide layer, the silicon nitride layer and the thermal oxide layer to define an intrinsic base and emitter area, thermally oxidizing the polycrystalline layer and driving the base impurity downwardly into the epitaxial layer, to form the intrinsic and extrinsic base regions of the transistor, isotropically etching the thermal oxide to expose the polysilicon layer in the emitter area while leaving the sidewall of the polycrystalline silicon layer covered with the thermal oxide, ion implanting an emitter impurity into the exposed emitter area of the polycrystalline silicon layer, thermally oxidizing the polycrystalline silicon layer in the emitter area to drive the emitter impurity inwardly into the epitaxial layer, and opening the collector, extrinsic base and emitter contact openings and forming conductive metallurgy.