Semiconductor memory device capable of relieving defective bits

Claim 2

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a plurality of well regions of a second conductivity type which are independently formed in said semiconductor substrate; a memory cell array having a plurality of memory cells each formed of a MOS transistor of the first conductivity type and a MOS transistor of the second conductivity type and arranged in an array form, said MOS transistors of the first conductivity type in each row being formed in a corresponding one of said plurality of well regions and said MOS transistors of the second conductivity type being formed in said semiconductor substrate; a plurality of common source wirings respectively connected to said plurality of well regions and each connected commonly to sources of those of the MOS transistors of the first conductivity type which are formed in a corresponding one of said plurality of well regions; and switching means for selectively supplying one of a power source potential and a potential of said semiconductor substrate to said common source wiring, said switching means supplying the power source potential to a well region on a row having no defective memory cell and supply the potential of said semiconductor substrate to a well region on a row having a defective memory cell.

Claim 3

A semiconductor memory device according to claim 1, wherein said memory cell array includes a static memory cell.

Claim 4

A semiconductor memory device according to claim 2, wherein said static memory cell includes a first CMOS inverter having input and output terminals; a second CMOS inverter having input and output terminals respectively connected to the output and input terminals of said first CMOS inverter; a first transfer MOS transistor whose current path is connected between a first bit line of a pair of bit lines and the output terminal of said first CMOS inverter and whose gate is connected to a word line; and a second transfer MOS transistor whose current path is connected between a second bit line of said pair of bit lines and the output terminal of said second CMOS inverter and whose gate is connected to said word line.

Claim 5

A semiconductor memory device according to claim 1, wherein said switching means includes a plurality of switching circuits respectively connected to said plurality of common source wirings, each of said switching circuits including a first MOS transistor of the first conductivity type whose current path is connected between a corresponding one of said common source wirings and a power source terminal; a second MOS transistor of the second conductivity type whose current path is connected between said corresponding one of said common source wirings and a ground terminal and whose gate is connected to the gate of said first MOS transistor; a CMOS inverter having an output terminal connected to the gates of said first and second MOS transistors; a third MOS transistor of the second conductivity type whose current path is connected between the input terminal of said CMOS inverter and said ground terminal and whose gate is connected to the output terminal of said CMOS inverter; and a fuse connected between the input terminal of said CMOS inverter and said power source terminal.

Claim 6

A semiconductor memory device according to claim 1, wherein said switching means includes a plurality of switching circuits respectively connected to said plurality of common source wirings, each of said switching circuits including a first MOS transistor of the first conductivity type whose current path is connected between a corresponding one of said common source wirings and a power source terminal; a second MOS transistor of the second conductivity type whose current path is connected between said corresponding one of said common source wirings and a ground terminal and whose gate is connected to the gate of said first MOS transistor; a fuse connected between a gate common connection node between the gates of said first and second MOS transistors and said power source terminal; a third MOS transistor of the second conductivity type whose current path is connected between said gate common connection node and said ground terminal; and a CMOS inverter having an input terminal connected to said gate common connection node and an output terminal connected to the gate of said third MOS transistor.

Claim 7

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a plurality of well regions of a second conductivity type which are independently formed in said semiconductor substrate; a memory cell array having a plurality of memory cells each formed of MOS transistors of the first conductivity type and MOS transistors of the second conductivity type and arranged in an array form, said MOS transistors of the first conductivity type of a plurality of rows being formed in a corresponding one of said plurality of well regions and said MOS transistors of the second conductivity type being formed in said semiconductor substrate; a plurality of common source wirings respectively connected to said plurality of well regions and each connected commonly to sources of those of the MOS transistors of the first conductivity type which are formed in a corresponding one of said plurality of well regions; and switching means for selectively supplying one of a power source potential and a potential of said semiconductor substrate to said common source wiring, said switching means supplying the power source potential to at least one of said plurality of well regions on a row having no defective memory cell and supplying the potential of said semiconductor substrate to the well region, at least one of said plurality of well regions on a row having a defective memory cell.

Claim 8

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a plurality of well regions of a second conductivity type which are independently formed in said semiconductor substrate; a memory cell array having a plurality of memory cells each formed of MOS transistors of the first conductivity type and MOS transistors of the second conductivity type and arranged in an array form, said MOS transistors of the first conductivity type of a plurality of rows being formed in a corresponding one of said plurality of well regions and said MOS transistors of the second conductivity type being formed in said semiconductor substrate; a plurality of common source wirings respectively connected to said plurality of well regions and each connected commonly to sources of those of the MOS transistors of the first conductivity type which are formed in a corresponding one of said plurality of well regions; and switching means for selectively supplying one of a power source potential and a potential of said semiconductor substrate to said common source wiring, said switching means supplying the power source potential to at least one of said plurality of well regions on a row having no defective memory cell and supplying the potential of said semiconductor substrate to the well region, at least one of said plurality of well regions on a row having a defective memory cell.

Claim 9

A semiconductor memory device according to claim 12, wherein said memory cell array includes a static memory cell.

Claim 10

A semiconductor memory device according to claim 7, wherein said static memory cell includes a first CMOS inverter having input and output terminals; a second CMOS inverter having input and output terminals respectively connected to the output and input terminals of said first CMOS inverter; a first transfer MOS transistor whose current path is connected between a first bit line of a pair of bit lines and the output terminal of said first CMOS inverter and whose gate is connected to a word line; and a second transfer MOS transistor whose current path is connected between a second bit line of said pair of bit lines and the output terminal of said second CMOS inverter and whose gate is connected to said word line.

Claim 11

A semiconductor memory device according to claim 6, wherein said switching means includes a plurality of switching circuits respectively connected to said plurality of common source wirings, each of said switching circuits including a first MOS transistor of the second conductivity type whose current path is connected between a corresponding one of said common source wirings and a power source terminal; a second MOS transistor of the first conductivity type whose current path is connected between said corresponding one of said common source wirings and a ground terminal and whose gate is connected to the gate of said first MOS transistor; a CMOS inverter having an output terminal connected to the gates of said first and second MOS transistors; a third MOS transistor of the first conductivity type whose current path is connected between the input terminal of said CMOS inverter and said ground terminal and whose gate is connected to the output terminal of said CMOS inverter; and a fuse connected between the input terminal of said CMOS inverter and said power source terminal.

Claim 12

A semiconductor memory device according to claim 6, wherein said switching means includes a plurality of switching circuits respectively connected to said plurality of common source wirings, each of said switching circuits including a first MOS transistor of the first conductivity type whose current path is connected between a corresponding one of said common source wirings and a power source terminal; a second MOS transistor of the second conductivity type whose current path is connected between said corresponding one of said common source wirings and a ground terminal and whose gate is connected to the gate of said first MOS transistor; a fuse connected between a gate common connection node between the gates of said first and second MOS transistors and said power source terminal; a third MOS transistor of the second conductivity type whose current path is connected between said gate common connection node and said ground terminal; and a CMOS inverter having an input terminal connected to said gate common connection node and an output terminal connected to the gate of said third MOS transistor.