Semiconductor memory device having improved redundant structure

Claim 2

A semiconductor memory device comprising a plurality of memory cell, said memory cells being divided into a plurality of sections, a major part of said sections being adapted to be accessed, the remaining part of said sections being inhibited from being accessed, means for receiving address information, means for accessing said major part of said sections, a common power supply line, and a plurality of branch power lines each provided for each of said sections and adapted to supply a power supply thereto, the branch power lines associated with said major part of said sections being electrically connected to said common power supply line, the branch power line or lines associated with said remaining part of said sections being electrically isolated from said common power supply line.

Claim 3

The memory device according to claim 1, in which each of said memory cells is of a flip-flop type.

Claim 4

The memory device according to claim 1, in which said memory cells are arranged in a matrix form of rows and columns and said sections are defined by the columns.

Claim 5

The memory device according to claim 1, in which each of said branch power lines is formed in connction with said common power supply line via a connecting portion and the connection portion of the branch power'line or lines associated with said remaining part of said sections being cut.

Claim 6

A semiconductor memory device comprising a main array of memory cells arranged in rows and columns, a redundant array of memory cells arranged in at least one row and columns, said redundant array of memory cells being used to replace a defective row having a defective memory cell in said main array of memory cells, said main array and redundant array sharing the columns in common, means for receiving row address information, means responsive to said row address information and redundant information about said defective row for selecting one of the rows of said main array and said redundant array except said defective row, means for receiving column address information, means responsive to said column address information for selecting said columns, a trunk power line, and a plurality of branch power lines each provided for each of the rows of said main array and said redundant array, the branch lines associated with the rows other than said defective row being electrically connected to said trunk power line thereby to supply a power supply to the memory cells belonging to the rows other than said defective row, the branch line associated with said defective row being electrically isolated from said trunk power line.

Claim 7

A semiconductor memory device comprising a main array of memory cells arranged in rows and columns, a redundant array of memory cells arranged in at least one row and columns, said redundant array of memory cells being used to replace a defective row having a defective memory cell in said main array of memory cells, said main array and redundant array sharing the columns in common, means for receiving row address information, means responsive to said row address information and redundant information about said defective row for selecting one of the rows of said main array and said redundant array except said defective row, means for receiving column address information, means responsive to said column address information for selecting said columns, a trunk power line, and a plurality of branch power lines each provided for each of the rows of said main array and said redundant array, the branch lines associated with the rows other than said defective row being electrically connected to said trunk power line thereby to supply a power supply to the memory cells belonging to the rows other than said defective row, the branch line associated with said defective row being electrically isolated from said trunk power line.

Claim 8

The memory device according to'claim 5, in which each of said memory cells includes a flip-flop circuit and a pair of transfer gate transistors for connecting a pair of input/output nodes of said flip-flop circuit to a pair of digit lines, the gates of said transfer gate transistors being connected to a word line.

Claim 9

The memory device according to claim 5, in which a word line is arranged in each of the rows and a pair of digit lines are arranged in each of the columns.

Claim 10

The memory device according to claim 5, in which each of said branch power lines is connected to the memory cells of the same row.