Patent US5097311A successfully refreshed from Google Patents.
US5097311A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Toshiba Corp
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Filing: 1989-07-05
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Granted: 1992-03-17
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Expires: 2009-07-05
Abstract
Abstract A CMOS inverter circuit incorporating a P channel MOSFET and an N channel MOSFET, both of which can achieve surface conduction, is provided while maintaining the prescribed miniaturization. Thus, the threshold value and conductance of the both MOSFETs are independent of the thickness of the silicon film, and can be easily controlled in the manufacturing processes thereof.
Inventors
- 👤 Masao Iwase
- 👤 Sanae Fukuda
- 👤 Makoto Yoshimi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:55
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/8311
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
226 words
A semiconductor device, comprising: a semiconductor substrate having a substantially planar surface; means for applying a bias potential to said semiconductor substrate; an insulating film on said semiconductor substrate; a first conductive-type region having a low-impurity concentration on said insulating film; a gate-insulating film on said first conductive-type region; a gate electrode on said gate-insulating film; first conductive-type source and drain regions, each having a high-impurity concentration, said first source and drain regions sandwiching the first conductive-type region; second conductive-type source and drain regions, each having a high-impurity concentration, said second source and drain regions sandwiching said first conductive-type region, said second source and drain regions being on a line perpendicular to a line connecting said first source and drain regions; and an electrode on each said source and drain region; wherein a thickness W of said first conductive-type region in a direction perpendicular to the planar surface of the substrate is smaller than a value obtained from the following equation, ##EQU6## where V'fb=the energy difference in Fermi levels between said first conductive-type region and said semiconductor substrate, ε'=the dielectric constant of said first conductive-type region, ε ox=the dielectric constant of said insulating film, Tbox=the thickness of said insulating film, q=electron charge, Csub=the impurity concentration in said first conductive-type region, and Vsub=the substrate potential at the surface of said first conductive-type region closest to the substrate.
Claim 2
Dependent Claim
226 words
A semiconductor device, comprising: a semiconductor substrate having a substantially planar surface; means for applying a bias potential to said semiconductor substrate; an insulating film on said semiconductor substrate; a first conductive-type region having a low-impurity concentration on said insulating film; a gate-insulating film on said first conductive-type region; a gate electrode on said gate-insulating film; first conductive-type source and drain regions, each having a high-impurity concentration, said first source and drain regions sandwiching the first conductive-type region; second conductive-type source and drain regions, each having a high-impurity concentration, said second source and drain regions sandwiching said first conductive-type region, said second source and drain regions being on a line perpendicular to a line connecting said first source and drain regions; and an electrode on each said source and drain region; wherein a thickness W of said first conductive-type region in a direction perpendicular to the planar surface of the substrate is smaller than a value obtained from the following equation, ##EQU6## where V'fb=the energy difference in Fermi levels between said first conductive-type region and said semiconductor substrate, ε'=the dielectric constant of said first conductive-type region, ε ox=the dielectric constant of said insulating film, Tbox=the thickness of said insulating film, q=electron charge, Csub=the impurity concentration in said first conductive-type region, and Vsub=the substrate potential at the surface of said first conductive-type region closest to the substrate.
Claim 3
Dependent Claim
170 words
A semiconductor device, comprising: a semiconductor substrate having a substantially planar surface; means for applying a bias potential to said semiconductor substrate; an insulating film on said semiconductor substrate; a first conductive-type region having a low-impurity concentration on said insulating film; a gate-insulating film on said first conductive-type region; a gate electrode on said gate-insulating film; first conductive-type source and drain regions, each having a high-impurity concentration, said first source and drain regions sandwiching the first conductive-type region; second conductive-type source and drain regions, each having a high-impurity concentration, said second source and drain regions sandwiching said first conductive-type region, said second source and drain regions being on a line perpendicular to a line connecting said first source and drain regions; and an electrode on each said source and drain region; wherein a threshold voltage of a front side surface of the first conductive-type region contacting the gate insulating film is smaller than a threshold voltage of a back side surface of the first conductive-type region contacting the insulating film.
Claim 4
Dependent Claim
170 words
A semiconductor device, comprising: a semiconductor substrate having a substantially planar surface; means for applying a bias potential to said semiconductor substrate; an insulating film on said semiconductor substrate; a first conductive-type region having a low-impurity concentration on said insulating film; a gate-insulating film on said first conductive-type region; a gate electrode on said gate-insulating film; first conductive-type source and drain regions, each having a high-impurity concentration, said first source and drain regions sandwiching the first conductive-type region; second conductive-type source and drain regions, each having a high-impurity concentration, said second source and drain regions sandwiching said first conductive-type region, said second source and drain regions being on a line perpendicular to a line connecting said first source and drain regions; and an electrode on each said source and drain region; wherein a threshold voltage of a front side surface of the first conductive-type region contacting the gate insulating film is smaller than a threshold voltage of a back side surface of the first conductive-type region contacting the insulating film.
Claim 5
Dependent Claim
179 words
A semiconductor device, comprising: a semiconductor substrate having a substantially planar surface; means for applying a bias potential to said semiconductor substrate; an insulating film on said semiconductor substrate; a first conductive-type region having a low-impurity concentration on said insulating film; a gate-insulating film on said first conductive-type region; a gate electrode on said gate-insulating film; first conductive-type source and drain regions, each having a high-impurity concentration, said first source and drain regions sandwiching the first conductive-type region; second conductive-type source and drain regions, each having a high-impurity concentration, said second source and drain regions sandwiching said first conductive-type region, said second source and drain regions being on a line perpendicular to a line connecting said first source and drain regions; and an electrode on each said source and drain region; wherein said first conductive-type source and drain regions are P type regions, and said second conductive-type source and drain regions are N-type regions, and wherein a channel length between said P-type source and drain regions is smaller than a channel length between said N-type source and drain regions.
Claim 6
Dependent Claim
179 words
A semiconductor device, comprising: a semiconductor substrate having a substantially planar surface; means for applying a bias potential to said semiconductor substrate; an insulating film on said semiconductor substrate; a first conductive-type region having a low-impurity concentration on said insulating film; a gate-insulating film on said first conductive-type region; a gate electrode on said gate-insulating film; first conductive-type source and drain regions, each having a high-impurity concentration, said first source and drain regions sandwiching the first conductive-type region; second conductive-type source and drain regions, each having a high-impurity concentration, said second source and drain regions sandwiching said first conductive-type region, said second source and drain regions being on a line perpendicular to a line connecting said first source and drain regions; and an electrode on each said source and drain region; wherein said first conductive-type source and drain regions are P type regions, and said second conductive-type source and drain regions are N-type regions, and wherein a channel length between said P-type source and drain regions is smaller than a channel length between said N-type source and drain regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-17 | 1995-09-16 | 1996-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-17 | 1999-09-16 | 2000-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-17 | 2003-09-16 | 2004-03-17 | $7700.00 | Window Closed / Lapsed |