US5097148A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit buffer with improved drive capability
Assignee: Nokia Bell Labs
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Filing: 1990-04-25
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Granted: 1992-03-17
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Expires: 2010-04-25
Abstract
Abstract An output buffer provides for additional current sinking or sourcing capability by switching in an additional transistor when the output voltage passes a given level. This allows the output buffer to supply DC current to a load without requiring an excessively large AC drive capability, which could undesirably increase switching noise. In a typical embodiment, an inverter senses when the buffer output voltage reaches its switching threshold (approximately V DD /2), and turns on the additional transistor after a given delay. For example, a CMOS output buffer driving a TTL load may obtain additional current sinking capability by this technique. On-chip buffers (e.g., bus drivers and clock drivers) can also benefit from this technique.
Inventors
- 👤 Thaddeus J. Gabara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 03:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/003; H03K19/00346; H03K19/00361; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
126 words
An integrated circuit comprising a buffer including: a pull-up transistor for pulling the voltage on a buffer output node toward a first power supply voltage, and a pull-down transistor for pulling the voltage on said buffer output node toward a second power supply voltage; wherein the pull-up and pull-down transistors operate in response to a buffer input signal; characterized in that said buffer further comprises an additional transistor for pulling the voltage on the output node toward a given one of the first and second power supply voltages; and means connected to said buffer output node for causing said additional transistor to conduct when the voltage on said buffer output node passes a given threshold in the range between the first and second power supply voltages.
Claim 2
Dependent Claim
126 words
An integrated circuit comprising a buffer including: a pull-up transistor for pulling the voltage on a buffer output node toward a first power supply voltage, and a pull-down transistor for pulling the voltage on said buffer output node toward a second power supply voltage; wherein the pull-up and pull-down transistors operate in response to a buffer input signal; characterized in that said buffer further comprises an additional transistor for pulling the voltage on the output node toward a given one of the first and second power supply voltages; and means connected to said buffer output node for causing said additional transistor to conduct when the voltage on said buffer output node passes a given threshold in the range between the first and second power supply voltages.
Claim 3
Dependent Claim
48 words
The integrated circuit of claim 1 wherein said pull-up transistor is a p-channel field effect transistor having a source coupled to a positive power supply voltage node, and said pull-down transistor is a n-channel field effect transistor having a source coupled to a negative power supply voltage node.
Claim 4
Dependent Claim
22 words
The integrated circuit of claim 2 wherein said additional transistor is a n-channel field effect transistor that provides additional current sinking capability.
Claim 5
Dependent Claim
22 words
The integrated circuit of claim 2 wherein said additional transistor is a p-channel field effect transistor that provides additional current sourcing capability.
Claim 6
Dependent Claim
43 words
The integrated circuit of claim 2 wherein said means for causing said additional transistor to conduct comprises a CMOS inverter having a switching threshold in the range of from 0.2 to 0.8 of the difference of said first and second power supply voltages.
Claim 7
Dependent Claim
38 words
The integrated circuit of claim 5 wherein said means for causing said additional transistor to conduct comprises a CMOS inverter having a switching threshold of about one-half of the difference of said first and second power supply voltages.
Claim 8
Dependent Claim
46 words
The integrated circuit of claim 5 wherein said means for causing said additional transistor to conduct further comprises a delay means for allowing the buffer output voltage to transition within a given increment of said given power supply voltage before allowing said additional transistor to conduct.
Claim 9
Dependent Claim
26 words
The integrated circuit of claim 7 wherein said given increment is less than 25 percent of the difference of said first and second power supply voltages.
Claim 10
Dependent Claim
22 words
The integrated circuit of claim 1 wherein said buffer is an output buffer, with said output node being connected to a bondpad.
Claim 11
Dependent Claim
26 words
The integrated circuit of claim 1 wherein said buffer is an on-chip driver, wherein said output node is connected to a load on said integrated circuit.
Claim 12
Dependent Claim
141 words
An integrated circuit comprising a CMOS output buffer for driving TTL loads, said integrated circuit including: a p-channel pull-up transistor for pulling the voltage on a buffer output node toward a positive power supply voltage, and a n-channel pull-down transistor for pulling the voltage on said buffer output node toward a negative power supply voltage; wherein the pull-up and pull-down transistors operate in response to a buffer input signal; characterized in that said buffer further comprises an additional n-channel transistor for pulling the voltage on the output node toward the negative power supply voltage; and means including at least one inverter coupled to said buffer output node for causing said additional transistor to conduct when the voltage on said buffer output node passes a given threshold that is less than one-half the difference between the positive and negative power supply voltages.
Claim 13
Dependent Claim
141 words
An integrated circuit comprising a CMOS output buffer for driving TTL loads, said integrated circuit including: a p-channel pull-up transistor for pulling the voltage on a buffer output node toward a positive power supply voltage, and a n-channel pull-down transistor for pulling the voltage on said buffer output node toward a negative power supply voltage; wherein the pull-up and pull-down transistors operate in response to a buffer input signal; characterized in that said buffer further comprises an additional n-channel transistor for pulling the voltage on the output node toward the negative power supply voltage; and means including at least one inverter coupled to said buffer output node for causing said additional transistor to conduct when the voltage on said buffer output node passes a given threshold that is less than one-half the difference between the positive and negative power supply voltages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-17 | 1995-09-16 | 1996-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-17 | 1999-09-16 | 2000-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-17 | 2003-09-16 | 2004-03-17 | $7700.00 | Window Closed / Lapsed |