Variable frequency sine wave carrier signal generator

Claim 1

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, wherein said start signal and said second clock signal have varying rates with respect to each other so that an output coupled from said modulus generating means to said count input of said first settable counter means generates a succession of different modulus values at said first settable counter means, said first settable counter means thereby generating binary output signals of varying frequency and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency.

Claim 2

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, wherein said start signal and said second clock signal have varying rates with respect to each other so that an output coupled from said modulus generating means to said count input of said first settable counter means generates a succession of different modulus values at said first settable counter means, said first settable counter means thereby generating binary output signals of varying frequency and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency.

Claim 9

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, and an output coupled to said count input of said first settable counter means for generating a succession of modulus values in response to receipt of a start signal and said second clock signal; and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency; wherein said modulus generating means includes a second counter means having an input serving as said clock input of said modulus generating means and an output, and memory means for storing said modulus values, said memory means having address inputs coupled to the output of said second counter means.

Claim 10

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, and an output coupled to said count input of said first settable counter means for generating a succession of modulus values in response to receipt of a start signal and said second clock signal; and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency; wherein said modulus generating means includes a second counter means having an input serving as said clock input of said modulus generating means and an output, and memory means for storing said modulus values, said memory means having address inputs coupled to the output of said second counter means.

Claim 11

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, and an output coupled to said count input of said first settable counter means for generating a succession of modulus values in response to receipt of a start signal and said second clock signal; and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency; second clock generating means, said second clock generating means including an oscillator and a second settable counter means having a clock input coupled to said oscillator, a count input terminal means for receiving said rate signal, and an output terminal means coupled to said clock input of said modulus generating means, the output of said second settable counter means having a frequency determined by the value of said rate signal.

Claim 12

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, and an output coupled to said count input of said first settable counter means for generating a succession of modulus values in response to receipt of a start signal and said second clock signal; and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency; second clock generating means, said second clock generating means including an oscillator and a second settable counter means having a clock input coupled to said oscillator, a count input terminal means for receiving said rate signal, and an output terminal means coupled to said clock input of said modulus generating means, the output of said second settable counter means having a frequency determined by the value of said rate signal.

Claim 13

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, and an output coupled to said count input of said first settable counter means for generating a succession of modulus values in response to receipt of a start signal and said second clock signal; and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency; wherein said modulus generating means includes second counter means having an input serving as said clock input of said modulus generating means and said output, first memory means for storing a first plurality of modulus determining values, second memory means for storing a second plurality of modulus determining values, said first and second memory means having address inputs coupled to the output of said second counter means and outputs, and processing means having inputs coupled tosaid outputs of said first and second memory means for generating said modulus values from said modulus determining values.

Claim 14

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, and an output coupled to said count input of said first settable counter means for generating a succession of modulus values in response to receipt of a start signal and said second clock signal; and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency; wherein said modulus generating means includes second counter means having an input serving as said clock input of said modulus generating means and said output, first memory means for storing a first plurality of modulus determining values, second memory means for storing a second plurality of modulus determining values, said first and second memory means having address inputs coupled to the output of said second counter means and outputs, and processing means having inputs coupled tosaid outputs of said first and second memory means for generating said modulus values from said modulus determining values.

Claim 15

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, and an output coupled to said count input of said first settable counter means for generating a succession of modulus values in response to receipt of a start signal and said second clock signal; and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency; wherein said converting means includes: a first low pass filter means for smoothing the binary output signals from said first settable counter means; means for generating a sine wave signal having a frequency different from the frequency of the signals output from said first low pass filter means; mixer means having a first input coupled to the output of said first low pass filter means, a second input coupled to the output of said sine wave signal generating means, and an output; and second low pass filter means having an input coupled to the output of said mixer means and an outlet for passing signals having frequencies lying within said predetermined spectral frequency limit.

Claim 16

A system for generating a variable frequency sine wave carrier signal in response to a start signal and a rate signal, said carrier signal having frequencies lying within a predetermined spectral frequency limit, said system comprising: first settable counter means having a clock input for receiving a first clock signal, a count input for receiving modulus value signals for establishing the counter modulus N, and an output terminal for manifesting a binary output signal having a frequency determined by the modulus N and said first clock signal; modulus generating means having a control input for receiving said start signal, a clock input for receiving a second clock signal, and an output coupled to said count input of said first settable counter means for generating a succession of modulus values in response to receipt of a start signal and said second clock signal; and means having an input coupled to the output terminal of said first settable counter means for converting the binary output signals therefrom to analog sine signals of variable frequency; wherein said converting means includes: a first low pass filter means for smoothing the binary output signals from said first settable counter means; means for generating a sine wave signal having a frequency different from the frequency of the signals output from said first low pass filter means; mixer means having a first input coupled to the output of said first low pass filter means, a second input coupled to the output of said sine wave signal generating means, and an output; and second low pass filter means having an input coupled to the output of said mixer means and an outlet for passing signals having frequencies lying within said predetermined spectral frequency limit.