US4484296A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase programmable signal generator means
Assignee: Boeing North American Inc
•
Filing: 1982-07-19
•
Granted: 1984-11-20
•
Expires: 2002-07-19
Abstract
Abstract A phase controlled signal generator using a cyclical counter with preset and reset control terminals to provide a continually advancing digital signal. This digital signal is converted in a sine table PROM and D to A converter to a sine wave signal which signal has a phase shift with respect to a reference in accordance with a phase control preset input and which signal can be periodically synchronized to a given starting phase to maintain signal stability or Doppler frequency shift.
Inventors
- 👤 Jan E. Treise
- 👤 Orville K. Nyhus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:59
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/22; H03L7/23; G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0328
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
156 words
Phase programmable signal generator means comprising, in combination: first means for supplying a clock signal; signal supply second means for supplying a phase control signal; third means for supplying a synchronizing signal; counter means including phase control signal input means, synchronizing signal input means, clock signal input means and digital output signal means for supplying digital output signals which change when a clock signal is applied to said clock signal input means and which change in relative phase in accordance with signals received at said phase control signal input means; means for receiving signals from said first, second, and third means at appropriate inputs of said counter means, the synchronizing signal acting to resynchronize the counter output signal after phase shift changes; and conversion means, connected to said digital output signal means of said counter means, for changing received digital output signals to an analog representation of a trigonometric function of the received digital number signal.
Claim 2
Dependent Claim
156 words
Phase programmable signal generator means comprising, in combination: first means for supplying a clock signal; signal supply second means for supplying a phase control signal; third means for supplying a synchronizing signal; counter means including phase control signal input means, synchronizing signal input means, clock signal input means and digital output signal means for supplying digital output signals which change when a clock signal is applied to said clock signal input means and which change in relative phase in accordance with signals received at said phase control signal input means; means for receiving signals from said first, second, and third means at appropriate inputs of said counter means, the synchronizing signal acting to resynchronize the counter output signal after phase shift changes; and conversion means, connected to said digital output signal means of said counter means, for changing received digital output signals to an analog representation of a trigonometric function of the received digital number signal.
Claim 3
Dependent Claim
63 words
Apparatus as claimed in claim 1 wherein said conversion means comprises: sine table look-up means for converting said digital output signals into digital sine function representation signals; digital-to-analog conversion means for converting the sine function representation signals to a multiple step function approximation of a sine-wave signal; and filter means for filtering the converted signal to a stepless representation of a sine-wave signal.
Claim 4
Independent Claim
59 words
The method of generating a phase controlled signal comprising the steps of: supplying clock input signals; supplying a phase control offset signal; outputting a digital output signal which cyclically resets to zero as an accumulated sum of clock and phase offset signals; and converting said digital output signal in accordance with a sine function to an analog output signal.
Claim 5
Independent Claim
59 words
The method of generating a phase controlled signal comprising the steps of: supplying clock input signals; supplying a phase control offset signal; outputting a digital output signal which cyclically resets to zero as an accumulated sum of clock and phase offset signals; and converting said digital output signal in accordance with a sine function to an analog output signal.
Claim 6
Dependent Claim
97 words
Apparatus for generating a phase controlled signal comprising, in combination: first means for supplying clock input signals; signal supply second means for supplying a phase control offset signal; third means, connected to said first and second means for receiving input signals therefrom and for outputting a digital output signal which cyclically resets to zero as an accumulated sum of clock and phase offset signals; and fourth means, connected to said third means for receiving said digital output signal therefrom and for converting said digital output signal in accordance with a sine function to an analog output signal.
Claim 7
Dependent Claim
97 words
Apparatus for generating a phase controlled signal comprising, in combination: first means for supplying clock input signals; signal supply second means for supplying a phase control offset signal; third means, connected to said first and second means for receiving input signals therefrom and for outputting a digital output signal which cyclically resets to zero as an accumulated sum of clock and phase offset signals; and fourth means, connected to said third means for receiving said digital output signal therefrom and for converting said digital output signal in accordance with a sine function to an analog output signal.
Claim 8
Independent Claim
60 words
The method of generating a phase controllable signal comprising the steps of: supplying clock input signals; supplying a phase control signal; outputting a digital output signal which cycles between given minimum and maximum values as an accumulated sum of clock and phase signals; and converting said digital output signal in accordance with a trigonometric function to an analog output signal.
Claim 9
Independent Claim
60 words
The method of generating a phase controllable signal comprising the steps of: supplying clock input signals; supplying a phase control signal; outputting a digital output signal which cycles between given minimum and maximum values as an accumulated sum of clock and phase signals; and converting said digital output signal in accordance with a trigonometric function to an analog output signal.
Claim 10
Dependent Claim
98 words
Apparatus for generating a phase controllable signal comprising, in combination: first means for supplying clock input signals; signal supply second means for supplying a phase control signal; third means, connected to said first and second means for receiving input signals therefrom and for outputting a digital output signal which cycles between predetermined minimum and maximum values as an accumulated sum of clock and phase signals; and fourth means, connected to said third means for receiving said digital output signal therefrom and for converting said digital output signal in accordance with a trigonometric function to an analog output signal.
Claim 11
Dependent Claim
98 words
Apparatus for generating a phase controllable signal comprising, in combination: first means for supplying clock input signals; signal supply second means for supplying a phase control signal; third means, connected to said first and second means for receiving input signals therefrom and for outputting a digital output signal which cycles between predetermined minimum and maximum values as an accumulated sum of clock and phase signals; and fourth means, connected to said third means for receiving said digital output signal therefrom and for converting said digital output signal in accordance with a trigonometric function to an analog output signal.
Claim 12
Dependent Claim
144 words
Apparatus for simulating a multifrequency field environment condition comprising, in combination: clock means for supplying a first clock signal; a plurality of phase lock loop means, each of said phase lock loop means including at least one clock signal output means for supplying a modified clock signal and reference signal input means connected to said clock means for receiving said first clock signal therefrom; a plurality of phase controlled signal generator means, including phase preset signal input means, clock input means and digital signal output means, connected to receive modified clock signals from corresponding ones of said phase lock loop; means for supplying phase reference synchronizing signals to said plurality of generator means from one of said phase lock loop means; and a plurality of phase preset signal supply means, connected to corresponding inputs of said generator means, for supplying phase preset signals thereto.
Claim 13
Dependent Claim
144 words
Apparatus for simulating a multifrequency field environment condition comprising, in combination: clock means for supplying a first clock signal; a plurality of phase lock loop means, each of said phase lock loop means including at least one clock signal output means for supplying a modified clock signal and reference signal input means connected to said clock means for receiving said first clock signal therefrom; a plurality of phase controlled signal generator means, including phase preset signal input means, clock input means and digital signal output means, connected to receive modified clock signals from corresponding ones of said phase lock loop; means for supplying phase reference synchronizing signals to said plurality of generator means from one of said phase lock loop means; and a plurality of phase preset signal supply means, connected to corresponding inputs of said generator means, for supplying phase preset signals thereto.
References Cited (Backward Citations)
US4172286A
Cited
US4134072A
Cited
US4192007A
Cited
US4346448A
Cited
US4349887A
Cited
US4410955A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-20 | 1988-05-21 | 1988-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-20 | 1992-05-21 | 1992-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-20 | 1996-05-21 | 1996-11-20 | $7700.00 | Window Closed / Lapsed |