US4748640A
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Digital circuit with band limiting characteristics for modem
Assignee: MICROCHIP ACQUISITION Corp
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Filing: 1986-02-21
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Granted: 1988-05-31
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Expires: 2006-02-21
Abstract
Abstract The input digital signal is applied to a transition detector which causes an up/down counter to increment or decrement each time a transition is detected. The output of the counter is utilized to address a read only memory (ROM) which, in turn, generates binary words representing first and second integers. These binary words are used to control a programmable divider to generate an output having a frequency which moves between two values corresponding to the digital input. The rate at which the frequency changes between the two values is controlled by the ROM contents. In the implementation, the frequency changes with a raised cosine shape.
Inventors
- 👤 Peter Staley
- 👤 David Coyne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:25
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03828; H04L25/03834; G; G06; G06F; G06F7/00; G06F7/60; G06F7/62; H03; H03K; H03K4/00; H03K4/02; H03K4/026; H03K4/94; H03K5/00; H03K5/00006
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
323 words
A circuit for generating an output whose frequency is a function of an input digital signal comprising means for receiving the input digital signal and for generating an intermediate signal in response to each transition in said input digital signal, said intermediate signal commencing at one of two preselected values and, upon detection of each transition in said input digital signal, incrementing or decrementing towards the other of said values, means for generating a reference frequency, means for dividing said reference frequency by a divisor which is a function of the value of said intermediate signal, the output of said dividing means having a frequency which is a function of the input digital signal, said intermediate signal generating means comprising means for generating a first control signal upon detection of a leading edge transition in said input digital signal and means for generating a second control signal upon detection of a trailing edge transition in said input digital signal, a reversible shift register connected as an up/down counter and wherein said first control signal causes said reversible shift register to shift in one direction and said second control signal causes said reversible shift register to shift in an opposite direction, said dividing means comprising memory means comprising a plurality of storage locations and means for addressing said storage locations in accordance with an output of said reversible shift register, said memory means generating first and second words, each of said words representing an integer, said dividing means further comprising counter means, counter control means, said counter control means receiving said reference frequency and controlling the count of said counter means in accordance therewith, means for applying one of said words to the data input of said counter means, overflow rate multiplier means, said overflow rate multiplier means receiving said other of said words and controlling said counter control means in accordance therewith, said overflow rate multiplier means comprising latch and full adder means.
Claim 2
Dependent Claim
323 words
A circuit for generating an output whose frequency is a function of an input digital signal comprising means for receiving the input digital signal and for generating an intermediate signal in response to each transition in said input digital signal, said intermediate signal commencing at one of two preselected values and, upon detection of each transition in said input digital signal, incrementing or decrementing towards the other of said values, means for generating a reference frequency, means for dividing said reference frequency by a divisor which is a function of the value of said intermediate signal, the output of said dividing means having a frequency which is a function of the input digital signal, said intermediate signal generating means comprising means for generating a first control signal upon detection of a leading edge transition in said input digital signal and means for generating a second control signal upon detection of a trailing edge transition in said input digital signal, a reversible shift register connected as an up/down counter and wherein said first control signal causes said reversible shift register to shift in one direction and said second control signal causes said reversible shift register to shift in an opposite direction, said dividing means comprising memory means comprising a plurality of storage locations and means for addressing said storage locations in accordance with an output of said reversible shift register, said memory means generating first and second words, each of said words representing an integer, said dividing means further comprising counter means, counter control means, said counter control means receiving said reference frequency and controlling the count of said counter means in accordance therewith, means for applying one of said words to the data input of said counter means, overflow rate multiplier means, said overflow rate multiplier means receiving said other of said words and controlling said counter control means in accordance therewith, said overflow rate multiplier means comprising latch and full adder means.
Claim 3
Dependent Claim
68 words
The circuit of claim 1, wherein said intermediate signal generating means comprises a transition detector, timing signal means, and counter means, said transition detector receiving said input digital signal and generating a control signal for each detected transition, said counter means receiving said timing signals and said control signals and counting from one of said values to the other of said values upon receipt of each control signal.
Claim 4
Dependent Claim
26 words
The circuit of claim 2, wherein said counter means generates a series of binary words representing quantities between said values upon the detection of each transition.
Claim 5
Dependent Claim
28 words
The circuit of claim 3, wherein said dividing means comprises a memory addressable by said binary words and capable, in accordance with the address, of generating said divisor.
Claim 6
Dependent Claim
33 words
The circuit of claim 2, wherein said counter means comprises a reversible pseudo random shift register and wherein the receipt of each control signal causes said register to count in the opposite direction.
Claim 7
Dependent Claim
13 words
The circuit of claim 1, wherein said divisor comprises first and second integers.
Claim 8
Dependent Claim
14 words
The circuit of claim 6, wherein said integers each comprises a four-bit binary word.
Claim 9
Dependent Claim
66 words
The circuit of claim 1, wherein said full adder means comprises a plurality of full adder circuits and wherein each of said full adder circuits has a carry output and a sum output, each of said carry outputs being operably connected to an input of an adjacent full adder circuit and each of said sum outputs being operably connected to different input of said latch means.
Claim 10
Dependent Claim
24 words
The circuit of claim 1, wherein the frequency of the output, when plotted against time, substantially comprises a portion of a raised cosine waveform.
Claim 11
Dependent Claim
176 words
Apparatus for band limiting FSK or PSK input signals comprising means for detecting each transition in the input signal and for generating a control signal coincident therewith, means for generating timing signals, means for counting said timing signals, said counting means counting in different directions between first and second preselected values in accordance with said control signals, storage means containing information relating to possible divisors, said storage means being operatively connected to be addressed by the output of said counting means and to generate a divisor in accordance therewith, means for generating a reference frequency, divider means operatively connected to said storage means to receive said divisor and divide said reference frequency thereby, said divisor comprising first and second words, said divider means comprising means programmable to divide said reference frequency by each of said first and second words and to take the average thereof, said divider means comprising a loadable psuedo random counter, a counter control circuit connected to said pseudo random counter and overflow rate multiplier means operably connected to said counter control circuit.
Claim 12
Dependent Claim
176 words
Apparatus for band limiting FSK or PSK input signals comprising means for detecting each transition in the input signal and for generating a control signal coincident therewith, means for generating timing signals, means for counting said timing signals, said counting means counting in different directions between first and second preselected values in accordance with said control signals, storage means containing information relating to possible divisors, said storage means being operatively connected to be addressed by the output of said counting means and to generate a divisor in accordance therewith, means for generating a reference frequency, divider means operatively connected to said storage means to receive said divisor and divide said reference frequency thereby, said divisor comprising first and second words, said divider means comprising means programmable to divide said reference frequency by each of said first and second words and to take the average thereof, said divider means comprising a loadable psuedo random counter, a counter control circuit connected to said pseudo random counter and overflow rate multiplier means operably connected to said counter control circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-31 | 1991-11-30 | 1992-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-31 | 1995-11-30 | 1996-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-31 | 1999-11-30 | 2000-05-31 | $7700.00 | Window Closed / Lapsed |