Conductivity modulated mosfet

Claim 2

A conductivity modulated metal oxide semiconductor field effect transistor, comprising: a semiconductor substrate of a first conductivity type which has first and second surfaces; a high resistance semiconductor layer of a second conductivity type which is formed on said first surface of said semiconductor substrate and has a high resistance; a base layer of the first conductivity type which is formed in said high resistance semiconductor layer; a source layer of the second conductivity type which is formed in said base layer; a gate electrode formed on a gate insulating film which is formed on said high resistance semiconductor layer and a channel region, said channel region being formed in said base layer between said high resistance semiconductor layer and said source layer; a source electrode ohmic-contacting said source layer and said base layer; and a drain electrode formed on said second surface of said semiconductor substrate; wherein when a total channel width within a unit area (1 cm 2 ) of an active region is W (μm), an area of the high resistance semiconductor layer which is formed beneath the gate electrode and is in direct contact with the gate insulating film within said unit area of the active region is SG (μm 2 ), a perimeter of said area SG within said unit area of the active region is T(μm), a channel length is l(μm) and a thickness of said gate insulating film is d(μm), a condition (W·SG)/(T·l·d)<1.46×10 8 is satisfied; wherein said gate electrode comprises a polycrystalline silicon film and a metal formed on a portion of said polycrystalline silicon film, said base layer of the first conductivity type being formed under said metal film.

Claim 3

A conductivity modulated metal oxide semiconductor field effect transistor, comprising: a semiconductor substrate of a first conductivity type which has first and second surfaces; a high resistance semiconductor layer of a second conductivity type which is formed on said first surface of said semiconductor substrate and has a high resistance; a base layer of the first conductivity type which is formed in said high resistance semiconductor layer; a source layer of the second conductivity type which is formed in said base layer; a gate electrode formed on a gate insulating film which is formed on said high resistance semiconductor layer and a channel region, said channel region being formed in said base layer between said high resistance semiconductor layer and said source layer; a source electrode ohmic-contacting said source layer and said base layer; and a drain electrode formed on said second surface of said semiconductor substrate; wherein when a total channel width within a unit area (1 cm 2 ) of an active region is W (μm), an area of the high resistance semiconductor layer which is formed beneath the gate electrode and is in direct contact with the gate insulating film within said unit area of the active region is SG (μm 2 ), a perimeter of said area SG within said unit area of the active region is T(μm), a channel length is l(μm) and a thickness of said gate insulating film is d(μm), a condition (W·SG)/(T·l·d)<1.46×10 8 is satisfied; wherein a lifetime killer is introduced in said high resistance semiconductor layer to decrease a saturation current of said transistor; wherein portions of said high resistance semiconductor layer are surrounded by said base layer to constitute island regions.

Claim 4

A conductivity modulated metal oxide semiconductor field effect transistor, comprising: a semiconductor substrate of a first conductivity type which has first and second surfaces; a high resistance semiconductor layer of a second conductivity type which is formed on said first surface of said semiconductor substrate and has a high resistance; a base layer of the first conductivity type which is formed in said high resistance semiconductor layer; a source layer of the second conductivity type which is formed in said base layer; a gate electrode formed on a gate insulating film which is formed on said high resistance semiconductor layer and a channel region, said channel region being formed in said base layer between said high resistance semiconductor layer and said source layer; a source electrode ohmic-contacting said source layer and said base layer; and a drain electrode formed on said second surface of said semiconductor substrate; wherein when a total channel width within a unit area (1 cm 2 ) of an active region is W (μm), an area of the high resistance semiconductor layer which is formed beneath the gate electrode and is in direct contact with the gate insulating film within said unit area of the active region is SG (μm 2 ), a perimeter of said area SG within said unit area of the active region is T(μm), a channel length is l(μm) and a thickness of said gate insulating film is d(μm), a condition (W·SG)/(T·l·d)<1.46×10 8 is satisfied; wherein a lifetime killer is introduced in said high resistance semiconductor layer to decrease a saturation current of said transistor; wherein portions of said high resistance semiconductor layer are surrounded by said base layer to constitute island regions.

Claim 5

The transistor according to claim 2, wherein said portions have rectangular shapes.

Claim 6

The transistor according to claim 2, wherein said gate electrode comprises a polycrystalline silicon film formed to cover said island regions and a metal film formed on a portion of said polycrystalline silicon film, said base layer of the first conductivity type being formed under said metal film to isolate said island regions.

Claim 7

A conductivity modulated metal oxide semiconductor field effect transistor, comprising: a semiconductor substrate of a first conductivity type which has first and second surfaces; a high resistance semiconductor layer of a second conductivity type which is formed on said first surface of said semiconductor substrate and has a high resistance; a base layer of the first conductivity type which is formed in said high resistance semiconductor layer; a source layer of the second conductivity type which is formed in said base layer; a gate electrode formed on a gate insulating film which is formed on said high resistance semiconductor layer and a channel region, said channel region being formed in said base layer between said high resistance semiconductor layer and said source layer; a source electrode ohmic-contacting said source layer and said base layer; and a drain electrode formed on said second surface of said semiconductor substrate; wherein when a total channel width within a unit area (1 cm 2 ) of an active region is W (μm), an area of the high resistance semiconductor layer which is formed beneath the gate electrode and is in direct contact with the gate insulating film within said unit area of the active region is SG (μm 2 ), a perimeter of said area SG within said unit area of the active region is T(μm), a channel length is l(μm) and a thickness of said gate insulating film is d(μm), a condition (W·SG)/(T·l·d)<1.46×10 8 is satisfied; wherein said channel region comprises a plurality of sections arranged orderly at regular intervals; and a plurality of regions having an impurity concentration higher than that of said plurality of regions being arranged between adjacent of said sections.

Claim 8

A conductivity modulated metal oxide semiconductor field effect transistor, comprising: a semiconductor substrate of a first conductivity type which has first and second surfaces; a high resistance semiconductor layer of a second conductivity type which is formed on said first surface of said semiconductor substrate and has a high resistance; a base layer of the first conductivity type which is formed in said high resistance semiconductor layer; a source layer of the second conductivity type which is formed in said base layer; a gate electrode formed on a gate insulating film which is formed on said high resistance semiconductor layer and a channel region, said channel region being formed in said base layer between said high resistance semiconductor layer and said source layer; a source electrode ohmic-contacting said source layer and said base layer; and a drain electrode formed on said second surface of said semiconductor substrate; wherein when a total channel width within a unit area (1 cm 2 ) of an active region is W (μm), an area of the high resistance semiconductor layer which is formed beneath the gate electrode and is in direct contact with the gate insulating film within said unit area of the active region is SG (μm 2 ), a perimeter of said area SG within said unit area of the active region is T(μm), a channel length is l(μm) and a thickness of said gate insulating film is d(μm), a condition (W·SG)/(T·l·d)<1.46×10 8 is satisfied; wherein said channel region comprises a plurality of sections arranged orderly at regular intervals; and a plurality of regions having an impurity concentration higher than that of said plurality of regions being arranged between adjacent of said sections.