Method for programming mos and cmos rom memories

Claim 1

A method for programming VLSI MOS and CMOS ROM memories comprising a plurality of memory cells each having source and drain regions separated by a channel region and a gate region superimposed on said channel region, with the memory cells having a substantially common structure and being arranged in rows of cells each having its source region in common with the cell arranged on a side thereof and its drain region in common with the cell arranged on an opposite side thereof, the method comprising the steps of forming the gate regions on a substrate of semiconductor material having a first conductivity type, at least partially shielding substrate regions adjacent to the channel regions of the memory cells to be programmed to an always-off state and introducing doping ion species in said substrate for forming said source and drain regions having a second conductivity type, substantially opposite to said first conductivity type thereby obtaining non-doped substrate regions adjacent to the gate regions, wherein before introducing said doping ion species the memory cells to be programmed to the always-off state are covered with a mask which extends at least partially on the gate region and substantially on one side thereof after introduction of ion species the gate regions of programmed cells are spaced from adjacent common source regions.

Claim 2

A method for programming VLSI MOS and CMOS ROM memories comprising a plurality of memory cells each having source and drain regions separated by a channel region and a gate region superimposed on said channel region, with the memory cells having a substantially common structure and being arranged in rows of cells each having its source region in common with the cell arranged on a side thereof and its drain region in common with the cell arranged on an opposite side thereof, the method comprising the steps of forming the gate regions on a substrate of semiconductor material having a first conductivity type, at least partially shielding substrate regions adjacent to the channel regions of the memory cells to be programmed to an always-off state and introducing doping ion species in said substrate for forming said source and drain regions having a second conductivity type, substantially opposite to said first conductivity type thereby obtaining non-doped substrate regions adjacent to the gate regions, wherein before introducing said doping ion species the memory cells to be programmed to the always-off state are covered with a mask which extends at least partially on the gate region and substantially on one side thereof after introduction of ion species the gate regions of programmed cells are spaced from adjacent common source regions.

Claim 4

A method for programming VLSI MOS and CMOS ROM memories comprising a plurality of memory cells each having source and drain regions separated by a channel region and a gate region superimposed on said channel region, with the memory cells having a substantially common structure and being arranged in rows of cells each having its source region in common with the cell arranged on a side thereof and its drain region in common with the cell arranged on an opposite side thereof, the method comprising the steps of forming the gate regions on a substrate of semiconductor material having a first conductivity type, at least partially shielding substrate regions adjacent to the channel regions of the memory cells to be programmed to an always-off state and introducing doping ion species in said substrate for forming said source and drain regions having a second conductivity type, substantially opposite to said first conductivity type thereby obtaining non-doped substrate regions adjacent to the gate regions, wherein before introducing said doping ion species the memory cells to be programmed to the always-off state are covered with a mask which extends at least partially on the gate region and substantially on one side thereof thereby after introduction of ion species the gate regions of programmed cells are spaced from adjacent common drain regions.

Claim 5

A method for programming VLSI MOS and CMOS ROM memories comprising a plurality of memory cells each having source and drain regions separated by a channel region and a gate region superimposed on said channel region, with the memory cells having a substantially common structure and being arranged in rows of cells each having its source region in common with the cell arranged on a side thereof and its drain region in common with the cell arranged on an opposite side thereof, the method comprising the steps of forming the gate regions on a substrate of semiconductor material having a first conductivity type, at least partially shielding substrate regions adjacent to the channel regions of the memory cells to be programmed to an always-off state and introducing doping ion species in said substrate for forming said source and drain regions having a second conductivity type, substantially opposite to said first conductivity type thereby obtaining non-doped substrate regions adjacent to the gate regions, wherein before introducing said doping ion species the memory cells to be programmed to the always-off state are covered with a mask which extends at least partially on the gate region and substantially on one side thereof thereby after introduction of ion species the gate regions of programmed cells are spaced from adjacent common drain regions.

Claim 8

A method according to claims 1 or 3, with said memory cells being made simultaneously with CMOS devices comprising first MOS transistors with channels having said first conductivity type and second transistors with channels having said second conductivity type, said method comprising after said gate region forming step, a first substrate masking step for covering substrate regions intended for accommodating the first MOS transistors and the memory cells to be programmed to an always-off state, a first doping ion species introduction step for selectively imparting the second conductivity type in the substrate to form drain and source regions of the second transistors and of memory cells not be programmed to the always-off state, a second masking step for covering substrate regions accommodating the second transistors and the memory cells, and a second doping ion species introduction step for selectively imparting the first conductivity type in the substrate to form the source and drain regions of the first transistors.