Soi mos transistor with a substrate-source connection

Claim 2

An MOS transistor formed in a substantially rectangular insulated portion of a thin monocrystalline silicon layer on an insulator, said transistor comprising a drain region of a first conductivity type coated with a drain conductive layer, a substrate region of a second conductivity type coated with an insulating layer overlaid by a gate conductive layer, the first and second conductivity types differing from each other, a source region of the first conductivity type coated with a source conductive layer, said drain region, substrate region and source region being successively located in a longitudinally extending direction, a pair of highly doped lateral stripes of the second conductivity type extending in said longitudinal direction along opposite parallel edges of both the substrate region and source region, said stripe contacting said substrate and source regions and being contacted by said source conductive layer, the edges of the substrate region and the source region being on the same side of the silicon layer.

Claim 3

The MOS transistor of claim 1 wherein the conductive source layer is a metal silicide layer.

Claim 4

The MOS transistor of claim 1 wherein said insulated portion is dielectrically insulated, and wherein said lateral stripe is an overdoped region directly formed in a lateral portion of regions normally corresponding to the substrate region and the source region.

Claim 5

The transistor of claim 1 wherein the dopant in the stripe partially diffuses into lateral portions of the substrate region.

Claim 6

An MOS structure comprising an insulator carrying a thin monocrystalline silicon layer including a substantially rectangular insulated portion of the mesa-type so it is separated from other insulating regions of the transistor by a gap in said monocrystalline silicon layer, an MOS transistor formed in the insulated portion of the monocrystalline silicon layer, the MOS transistor including a drain region of a first conductivity type coated with a drain conductive layer, a substrate region of a second conductivity type coated with an insulating layer overlaid by a gate conductive layer, the first and second conductivity types differing from each other, a source region of the first conductivity type coated with a source conductive layer, said drain region, substrate region and source region being successively located in a longitudinally extending direction, at least one highly doped lateral stripe of the second conductivity type extending in said longitudinal direction along an edge of the substrate region and an edge of the source region, said stripe contacting said substrate and source regions and being contacted by said source conductive layer, said lateral stripe including at least a portion of a highly doped spacer consisting essentially of polycrystalline silicon, the edges of the substrate region and the source region being on the same side of the silicon layer.

Claim 7

An MOS structure comprising an insulator carrying a thin monocrystalline silicon layer including a substantially rectangular insulated portion of the mesa-type so it is separated from other insulating regions of the transistor by a gap in said monocrystalline silicon layer, an MOS transistor formed in the insulated portion of the monocrystalline silicon layer, the MOS transistor including a drain region of a first conductivity type coated with a drain conductive layer, a substrate region of a second conductivity type coated with an insulating layer overlaid by a gate conductive layer, the first and second conductivity types differing from each other, a source region of the first conductivity type coated with a source conductive layer, said drain region, substrate region and source region being successively located in a longitudinally extending direction, at least one highly doped lateral stripe of the second conductivity type extending in said longitudinal direction along an edge of the substrate region and an edge of the source region, said stripe contacting said substrate and source regions and being contacted by said source conductive layer, said lateral stripe including at least a portion of a highly doped spacer consisting essentially of polycrystalline silicon, the edges of the substrate region and the source region being on the same side of the silicon layer.

Claim 8

An MOS structure comprising an insulator carrying a thin monocrystalline silicon layer including a substantially rectangular insulated portion, an MOS transistor formed in the insulated portion of the monocrystalline silicon layer, the MOS transistor including a drain region of a first conductivity type coated with a drain conductive layer, a substrate region of a second conductivity type coated with an insulating layer overlaid by a gate conductive layer, the first and second conductivity types differing from each other, a source region of the first conductivity type coated with a source conductive layer, said drain region, substrate region and source region being successively located in a longitudinally extending direction, a pair of highly doped lateral stripes of the second conductivity type extending in said longitudinal direction along opposite parallel edges of both the substrate and source regions, said stripe contacting said substrate and source regions and being contacted by said source conductive layer, the edges of the substrate region and the source region being on the same side of the silicon layer.

Claim 9

An MOS structure comprising an insulator carrying a thin monocrystalline silicon layer including a substantially rectangular insulated portion, an MOS transistor formed in the insulated portion of the monocrystalline silicon layer, the MOS transistor including a drain region of a first conductivity type coated with a drain conductive layer, a substrate region of a second conductivity type coated with an insulating layer overlaid by a gate conductive layer, the first and second conductivity types differing from each other, a source region of the first conductivity type coated with a source conductive layer, said drain region, substrate region and source region being successively located in a longitudinally extending direction, a pair of highly doped lateral stripes of the second conductivity type extending in said longitudinal direction along opposite parallel edges of both the substrate and source regions, said stripe contacting said substrate and source regions and being contacted by said source conductive layer, the edges of the substrate region and the source region being on the same side of the silicon layer.

Claim 10

The structure of claim 6 wherein the conductive source layer is a metal silicide layer.

Claim 11

The structure of claim 6 wherein said insulated portion is of the mesa-type so it is separated from other insulating regions of the transistor by a gap in said monocrystalline silicon layer, and wherein said lateral stripe includes at least a portion of a highly doped silicon spacer.

Claim 12

The structure of claim 6 wherein said insulated portion is dielectrically insulated, and wherein said lateral stripe is an overdoped region directly formed in a lateral portion of regions normally corresponding to the substrate region and the source region.

Claim 13

The structure of claim 6 wherein dopant in the stripe partially diffuses into lateral portions of the substrate region.

Claim 14

The structure of claim 8 wherein said highly doped silicon spacer consists essentially of polycrystalline silicon.

Claim 15

The structure of claim 5 wherein the conductive source layer is a metal silicide layer.

Claim 16

The structure of claim 6 wherein said insulated portion is of the mesa-type so it is separated from other insulating regions of the transistor by a gap in said monocrystalline silicon layer, and wherein said lateral stripe includes at least a portion of a highly doped silicon spacer.

Claim 17

The structure of claim 13 wherein said highly doped silicon spacer consists essentially of polycrystalline silicon.

Claim 18

The structure of claim 5 wherein said insulated portion is dielectrically insulated, and wherein said lateral stripe is an overdoped region directly formed in a lateral portion of regions normally corresponding to the substrate region and the source region.

Claim 19

The structure of claim 5 wherein dopant in the stripe partially diffuses into lateral portions of the substrate region.

Claim 20

The structure of claim 5 wherein a pair of said stripes are provided, each of said stripes extending along opposite parallel edges of the substrate region and the source region.

Claim 21

The MOS transistor according to claim 1, wherein said insulated portion is of the mesa-type so it is separated from other insulating regions of the transistor by a gap in said monocrystalline silicon layer, and wherein said lateral stripe includes at least a portion of a highly doped silicon spacer.

Claim 22

The MOS transistor according to claim 18, wherein said highly doped silicon spacer consists essentially of polycrystalline silicon.

Claim 23

An MOS transistor formed in a substantially rectangular insulated portion of a thin monocrystalline silicon layer on an insulator, said transistor comprising a drain region of a first conductivity type coated with a drain conductive layer, a substrate region of a second conductivity type coated with an insulating layer overlaid by a gate conductive layer, the first and second conductivity types differing from each other, a source region of the first conductivity type coated with a source conductive layer, said drain region, substrate region and source region being successively located in a longitudinally extending direction, said insulated portion being of the mesa-type so it is separated from other insulating regions of the transistor by a gap in said monocrystalline silicon layer, at least one highly doped lateral stripe of the second conductivity type extending in said longitudinal direction along an edge of the substrate region and an edge of the source region, said stripe contacting said substrate and source regions and being contacted by said source conductive layer, said lateral stripe including at least a portion of a highly doped spacer consisting essentially of polycrystalline silicon, the edges of the substrate region and the source region being on the same side of the silicon layer.

Claim 24

An MOS transistor formed in a substantially rectangular insulated portion of a thin monocrystalline silicon layer on an insulator, said transistor comprising a drain region of a first conductivity type coated with a drain conductive layer, a substrate region of a second conductivity type coated with an insulating layer overlaid by a gate conductive layer, the first and second conductivity types differing from each other, a source region of the first conductivity type coated with a source conductive layer, said drain region, substrate region and source region being successively located in a longitudinally extending direction, said insulated portion being of the mesa-type so it is separated from other insulating regions of the transistor by a gap in said monocrystalline silicon layer, at least one highly doped lateral stripe of the second conductivity type extending in said longitudinal direction along an edge of the substrate region and an edge of the source region, said stripe contacting said substrate and source regions and being contacted by said source conductive layer, said lateral stripe including at least a portion of a highly doped spacer consisting essentially of polycrystalline silicon, the edges of the substrate region and the source region being on the same side of the silicon layer.

Claim 25

The transistor of claim 20 wherein the dopant in the stripe partially diffuses into lateral portions of the substrate region.

Claim 26

The transistor of claim 20 wherein a pair of said stripes are provided, each of said stripes extending along opposite parallel edges of the substrate region and the source region.

Claim 27

The MOS transistor according to claim 20, wherein the conductive source layer (11) is a metal silicide layer.

Claim 28

The MOS transistor according to claim 20, wherein said insulated portion is dielectrically insulated, and wherein said lateral stripe is an overdoped region directly formed in a lateral portion of regions normally corresponding to the substrate region and the source region.