US5087956A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1989-05-30
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Granted: 1992-02-11
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Expires: 2009-05-30
Abstract
Abstract An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.
Inventors
- 👤 Shuji Ikeda
- 👤 Satoshi Meguro
- 👤 Kotaro Nishimura
- 👤 Sho Yamamoto
- 👤 Nobuyoshi Tanimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:49
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
128 words
A memory cell structure formed on a semiconductor substrate having a flip-flop comprised of first and second inverters, output terminals of said first and second inverters being respectively connected to input terminals of said second and first inverters, each of said first and second inverters being comprised of a MISFET and a polysilicon film which is connected in series to said MISFET, said polysilicon film being connected to a first wiring line for supplying a first fixed potential to said memory cells and having a plurality of first regions of a first conductivity type, a second region which has higher resistivity than that of said first regions, and a third region of a second conductivity type, wherein said second and third regions are disposed between said first regions.
Claim 2
Dependent Claim
128 words
A memory cell structure formed on a semiconductor substrate having a flip-flop comprised of first and second inverters, output terminals of said first and second inverters being respectively connected to input terminals of said second and first inverters, each of said first and second inverters being comprised of a MISFET and a polysilicon film which is connected in series to said MISFET, said polysilicon film being connected to a first wiring line for supplying a first fixed potential to said memory cells and having a plurality of first regions of a first conductivity type, a second region which has higher resistivity than that of said first regions, and a third region of a second conductivity type, wherein said second and third regions are disposed between said first regions.
Claim 3
Dependent Claim
22 words
A memory cell structure according to claim 1, wherein said third region is disposed closer to said MISFET than said second region.
Claim 4
Dependent Claim
44 words
A memory cell structure according to claim 2, wherein said polysilicon film further includes a fourth region of the second conductivity type, said fourth region being formed between said second region and one of said first regions which is disposed adjacent to said MISFET.
Claim 5
Dependent Claim
38 words
A memory cell structure according to claim 1, wherein said first and second conductivity types are respectively n- and p- types, said first region being doped with n-type impurity and said third region being doped with p-type impurity.
Claim 6
Dependent Claim
42 words
A memory cell structure according to claim 4, wherein the n-type impurity concentration of said second region is lower than that of said first region, and the p-type impurity concentration of said second region is lower than that of said third region.
Claim 7
Dependent Claim
28 words
A memory cell structure according to claim 5, wherein the n-type impurity concentration of said first region is higher than the p-type impurity concentration of said third region.
Claim 8
Dependent Claim
16 words
A memory cell structure according to claim 6, wherein said second region is an intrinsic region.
Claim 9
Dependent Claim
25 words
A memory cell structure according to claim 1, wherein a data line is stacked over at least a part of said second and third regions.
Claim 10
Dependent Claim
28 words
A memory cell structure according to claim 8, wherein a gate electrode of said MISFET is disposed below at least a part of said second and third regions.
Claim 11
Dependent Claim
54 words
A memory cell structure according to claim 8, wherein said data line is one of complementary data lines, and wherein a pair of said complementary data lines are coupled to said memory cell and are stacked over at least a part of said second and third regions of said first and second inverters respectively.
Claim 12
Dependent Claim
27 words
A memory cell structure according to claim 1, wherein said first wiring line is a power supply voltage wiring and is made integrally with said polysilicon film.
Claim 13
Dependent Claim
152 words
A semiconductor memory device comprising: a memory cell, formed on a semiconductor substrate, including a flip-flop comprised of first and second inverters, output terminals of said first and second inverters being respectively connected to input terminals of said second and first inverters, each of said first and second inverters being comprised of a MISFET and a polysilicon film which is connected in series to said MISFET, said polysilicon film being connected to a first wiring line which serves to supply a power supply voltage to said memory cells and having a first region of a first conductivity type, a second region which has higher resistivity than that of said first region, and a third region of a second conductivity type; and a pair of complementary data lines coupled to said memory cell and stacked over at least a part of said second and third regions of said first and second inverters respectively.
Claim 14
Dependent Claim
152 words
A semiconductor memory device comprising: a memory cell, formed on a semiconductor substrate, including a flip-flop comprised of first and second inverters, output terminals of said first and second inverters being respectively connected to input terminals of said second and first inverters, each of said first and second inverters being comprised of a MISFET and a polysilicon film which is connected in series to said MISFET, said polysilicon film being connected to a first wiring line which serves to supply a power supply voltage to said memory cells and having a first region of a first conductivity type, a second region which has higher resistivity than that of said first region, and a third region of a second conductivity type; and a pair of complementary data lines coupled to said memory cell and stacked over at least a part of said second and third regions of said first and second inverters respectively.
Claim 15
Dependent Claim
44 words
A semiconductor memory device according to claim 12, wherein said first region is disposed closer to said first wiring line than at least said second and third regions, and said third region is disposed closer to said MISFET than at least said second region.
Claim 16
Dependent Claim
56 words
A semiconductor memory device according to claim 13, wherein said polysilicon film further includes a fourth region of the first conductivity type, said fourth region being formed on a side of said polysilicon film which is closer to said MISFET than said third region, and having the same impurity concentration as that of said first region.
Claim 17
Dependent Claim
45 words
A semiconductor memory device according to claim 14, wherein said polysilicon film further includes a fifth region of the second conductivity type, said fifth region being formed between said first and second regions and having the same impurity concentration as that of said third region.
Claim 18
Dependent Claim
38 words
A semiconductor memory device according to claim 12, wherein said first and second conductivity types are respectively n- and p- types, said first region being doped with n-type impurity and said third region being doped with p-type impurity.
Claim 19
Dependent Claim
42 words
A semiconductor memory device according to claim 16, wherein the n-type impurity concentration of said second region is lower than that of said first region, and the p-type impurity concentration of said second region is lower than that of said third region.
Claim 20
Dependent Claim
28 words
A semiconductor memory device according to claim 17, wherein the n-type impurity concentration of said first region is higher than the p-type impurity concentration of said third region.
Claim 21
Dependent Claim
32 words
A semiconductor memory device according to claim 18, wherein said complementary data lines extend in substantially the same direction as that of said second and third region of said polycrystalline silicon films.
Claim 22
Dependent Claim
16 words
A semiconductor memory device according to claim 18, wherein said second region is an intrinsic region.
Claim 23
Dependent Claim
28 words
A semiconductor memory device according to claim 12, wherein a gate electrode of said MISFET is disposed below at least a part of said second and third regions.
Claim 24
Dependent Claim
20 words
A semiconductor memory device according to claim 12, wherein said first wiring line is made integrally with said polysilicon film.
Claim 25
Dependent Claim
154 words
A semiconductor device including a static RAM cell each having cross-coupled first and second driver MISFET, first and second switching MISFETs being connected between said first and second driver MISFETs and complementary data lines and having their gate electrodes connected to a word line, and polysilicon films which are connected in series to said first and second driver MISFETs, each of said polysilicon film being connected to a first wiring line which serves to supply a power supply voltage to said cells and including a first region of a first conductivity type and a load element region, said load element region having a second region which has a higher resistivity than that of said first region, wherein said load element region further includes at least a third region of a second conductivity type, and wherein complementary data lines are stacked over at least a part of said load element region of said polysilicon films.
Claim 26
Dependent Claim
154 words
A semiconductor device including a static RAM cell each having cross-coupled first and second driver MISFET, first and second switching MISFETs being connected between said first and second driver MISFETs and complementary data lines and having their gate electrodes connected to a word line, and polysilicon films which are connected in series to said first and second driver MISFETs, each of said polysilicon film being connected to a first wiring line which serves to supply a power supply voltage to said cells and including a first region of a first conductivity type and a load element region, said load element region having a second region which has a higher resistivity than that of said first region, wherein said load element region further includes at least a third region of a second conductivity type, and wherein complementary data lines are stacked over at least a part of said load element region of said polysilicon films.
Claim 27
Dependent Claim
45 words
A semiconductor device according to claim 23, wherein said first region is disposed closer to said first wiring line than at least said second and third regions, said third region being disposed closer to said first and second MISFETs than at least said second region.
Claim 28
Dependent Claim
58 words
A semiconductor device according to claim 24, wherein said polysilicon film further includes a fourth region of the first conductivity type, said fourth region being formed on the side of said polysilicon film which is closer to said first and second MISFETs than said third region, and having the same impurity concentration as that of said first region.
Claim 29
Dependent Claim
44 words
A semiconductor device according to claim 25, wherein said polysilicon film further includes a fifth region of the second conductivity type, said fifth region being formed between said first and second regions and having the same impurity concentration as that of said third region.
Claim 30
Dependent Claim
37 words
A semiconductor device according to claim 23, wherein said first and second conductivity types are respectively n- and p- types, said first region being doped with n-type impurity and said third region being doped with p-type impurity.
Claim 31
Dependent Claim
41 words
A semiconductor device according to claim 27, wherein the n-type impurity concentration of said second region is lower than that of said first region, and the p-type impurity concentration of said second region is lower than that of said third region.
Claim 32
Dependent Claim
27 words
A semiconductor device according to claim 27, wherein the n-type impurity concentration of said first region is higher than the p-type impurity concentration of said third region.
Claim 33
Dependent Claim
25 words
A semiconductor device according to claim 29, wherein said complementary data lines extend in substantially the same direction as that of said load element regions.
Claim 34
Dependent Claim
15 words
A semiconductor device according to claim 29, wherein said second region is an intrinsic region.
Claim 35
Dependent Claim
38 words
A semiconductor device according to claim 31, wherein said third region has a predetermined p-type impurity concentration so as to enhance the threshold voltage of a parasitic MISFET having a channel region defined by said load element region.
Claim 36
Dependent Claim
62 words
A semiconductor device according to claim 31, wherein each of said complementary data lines is formed above said semiconductor substrate and is positioned so as to be substantially aligned over said load element regions of said polysilicon films such that a projection of each data line in the direction of said semiconductor substrate would fall on a load element region associated therewith.
Claim 37
Dependent Claim
32 words
A semiconductor device according to claim 23, wherein each of the gate electrodes of said first and second MISFETs is disposed below at least a part of said second and third regions.
Claim 38
Dependent Claim
19 words
A semiconductor device according to claim 23, wherein said first wiring line is made integrally with said polysilicon film.
Claim 39
Dependent Claim
16 words
A semiconductor device according to claim 23, wherein said load element regions are load resistor means.
Claim 40
Dependent Claim
22 words
A semiconductor device according to claim 36, wherein said complementary data lines are formed from a first level layer of metal layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-10 | 1995-08-12 | 1996-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-10 | 1999-08-12 | 2000-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-10 | 2003-08-12 | 2004-02-11 | $7700.00 | Window Closed / Lapsed |