Mosfet and fabrication method

Claim 1

A method of fabricating complementary p-channel and n-channel MOSFETS, the method comprising the steps of: (a) providing gate electrodes for complementary p-channel and n-channel MOSFETS, each gate electrode being located on a respective oxide layer which extends over a respective region of silicon doped with respectively, an n- or p-type impurity, the gate electrodes being separated by a region of isolation oxide; (b) forming on the gate electrodes and the adjacent exposed portions of the oxide layer an insulating layer which acts as a barrier to diffusion of impurities in silicon; (c) forming over the insulating layer an etchable layer composed of an insulating material; and (d) anisotropically etching the etchable layer to provide sidewall spacers of the etchable layer on the insulating layer and adjacent the gate electrodes; wherein the n-channel MOSFET is a lightly doped drain MOSFET and is fabricated by steps (e) to (i); (e) masking the n-regions of silicon; (f) implanting an n+ type dopant impurity into the unmasked p-region of silicon, the sidewall spacers in the p-region acting to mask against implantation portions of the p-region which are located under the said sidewall spacers; (g) isotropically etching the said sidewall spacers from the insulating layer; (h) implanting an n-type dopant impurity into the said portions of the p-regions; and (i) unmasking the n-region of silicon; and wherein the p-channel MOSFET is fabricated either before or after the n-channel MOSFET by steps (j) to (m); (j) masking the p-region of silicon; (k) implanting a p+ type dopant impurity into the unmasked n-region of silicon, the sidewall spaces in the n-region acting to mask against implantation portions of the n-region which are located under the said sidewall spaces; (l) unmasking the p-region of silicon; and (m) diffusing the p+ implant towards the respective gate thereby to produce a zero drain overlap p-channel MOSFET.

Claim 2

A method of fabricating complementary p-channel and n-channel MOSFETS, the method comprising the steps of: (a) providing gate electrodes for complementary p-channel and n-channel MOSFETS, each gate electrode being located on a respective oxide layer which extends over a respective region of silicon doped with respectively, an n- or p-type impurity, the gate electrodes being separated by a region of isolation oxide; (b) forming on the gate electrodes and the adjacent exposed portions of the oxide layer an insulating layer which acts as a barrier to diffusion of impurities in silicon; (c) forming over the insulating layer an etchable layer composed of an insulating material; and (d) anisotropically etching the etchable layer to provide sidewall spacers of the etchable layer on the insulating layer and adjacent the gate electrodes; wherein the n-channel MOSFET is a lightly doped drain MOSFET and is fabricated by steps (e) to (i); (e) masking the n-regions of silicon; (f) implanting an n+ type dopant impurity into the unmasked p-region of silicon, the sidewall spacers in the p-region acting to mask against implantation portions of the p-region which are located under the said sidewall spacers; (g) isotropically etching the said sidewall spacers from the insulating layer; (h) implanting an n-type dopant impurity into the said portions of the p-regions; and (i) unmasking the n-region of silicon; and wherein the p-channel MOSFET is fabricated either before or after the n-channel MOSFET by steps (j) to (m); (j) masking the p-region of silicon; (k) implanting a p+ type dopant impurity into the unmasked n-region of silicon, the sidewall spaces in the n-region acting to mask against implantation portions of the n-region which are located under the said sidewall spaces; (l) unmasking the p-region of silicon; and (m) diffusing the p+ implant towards the respective gate thereby to produce a zero drain overlap p-channel MOSFET.