Method of manufacturing an insulated gate field effect transistor

Claim 2

A single mask method utilizing self alignment of source regions for manufacturing insulated gate field effect transistors with reduced spacing comprising the steps of: (a) forming indentations in a first conductivity type semiconductor substrate, each such indentation representing a transistor location; (b) forming an insulating layer on surfaces of said indentations; (c) depositing gate material in said indentations; (d) depositing insulating material containing first conductivity type impurities in said indentations; (e) removing said insulating material from portions of said substrate adjacent to said indentations; and (f) laterally diffusing first conductivity type impurities from said insulating material in said indentations into adjacent semiconductor material to form source regions; whereby transistors may be manufactured reliably in closely spaced relationship in the absence of successive registration steps through use of self alignment to provide transistors with large current capacity resulting from reduced channel resistance and high density integration.

Claim 3

The method of claim 1 additionally comprising the step of forming a second conductivity type semiconductor region adjacent to said indentations and said source regions following step (c).

Claim 4

The method of claim 1 additionally comprising the step of forming a source electrode on the surface of the structure in contact with one or more of said source regions.

Claim 5

The method of claim 1 additionally comprising the step of forming a drain electrode on the surface of said first conductivity type semiconductor substrate opposite said indentations.

Claim 6

The method of claim 1 additionally comprising the step of forming a second conductivity type semiconductor region in an area adjoining a surface of said first conductivity type semiconductor substrate prior to forming said indentations in said area.

Claim 7

The method of claim 1 additionally comprising the step of forming a minority carrier injection layer below said first conductivity type semiconductor substrate.

Claim 8

A single mask method utilizing self alignment of source regions for manufacturing insulated gate field effect transistors with reduced spacing comprising the steps of: (a) forming indentations in an n-type semiconductor substrate, each such indentation representing a transistor location; (b) oxidizing surfaces of said indentations by thermal oxidation so as to form a silicon oxide film on the surfaces of said indentations; (c) depositing a polysilicon gate material in said indentations; (d) forming a p-type base region by diffusing impurities into the region between adjacent indentations; (e) depositing a phosphorus glass insulating material into said indentations, so as to encase said gate material; (f) removing said phosphorus glass insulating material from portions of said substrate adjacent to said indentations; (g) laterally diffusing impurities from said phosphorus glass insulating material in said indentations into said adjacent base region to form n-type source regions; (h) forming source electrodes on the surface of the resulting structure, in contact with one or more of said source regions and base regions; and (i) forming a drain electrode on a surface of said substrate opposite said indentations; whereby transistors may be manufactured reliably in closely spaced relationship with no need for registration steps, outside of electrode formation, through use of self alignment to provide transistors with large current capacity resulting from reduced channel resistance and high density integration.

Claim 9

A single mask method utilizing self alignment of source regions for manufacturing insulated gate field effect transistors with reduced spacing comprising the steps of: (a) forming indentations in an n-type semiconductor substrate, each such indentation representing a transistor location; (b) oxidizing surfaces of said indentations by thermal oxidation so as to form a silicon oxide film on the surfaces of said indentations; (c) depositing a polysilicon gate material in said indentations; (d) forming a p-type base region by diffusing impurities into the region between adjacent indentations; (e) depositing a phosphorus glass insulating material into said indentations, so as to encase said gate material; (f) removing said phosphorus glass insulating material from portions of said substrate adjacent to said indentations; (g) laterally diffusing impurities from said phosphorus glass insulating material in said indentations into said adjacent base region to form n-type source regions; (h) forming source electrodes on the surface of the resulting structure, in contact with one or more of said source regions and base regions; and (i) forming a drain electrode on a surface of said substrate opposite said indentations; whereby transistors may be manufactured reliably in closely spaced relationship with no need for registration steps, outside of electrode formation, through use of self alignment to provide transistors with large current capacity resulting from reduced channel resistance and high density integration.