Patent US5084843A successfully refreshed from Google Patents.
US5084843A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory having control means for preventing unauthorized erasure of a memory array portion
Assignee: Hitachi Ltd
•
Filing: 1990-04-24
•
Granted: 1992-01-28
•
Expires: 2010-04-24
Abstract
Abstract A volatile storage circuit for latching data is disposed outside a non-volatile memory array. Before a bulk erase of the memory array, some of the data items contained therein are transferred to and held by the storage circuit. The data items thus saved are rewritten to the non-volatile memory array after the bulk erase, or alternatively, on the basis of control data items transferred to the storage circuit, only regions designated by these data items are subjected to the bulk erase. Thus, in case of a bulk erase of an EEPROM, some of the stored data items can be preserved, so as to prevent illicit use of and maintain the integrity of the preserved data. Also the testing time of the data rewritten to the memory array is reduced because of the elimination of the need to test the memory area containing the preserved data in that only the integrity of the memory area containing data sourced externally need be tested.
Inventors
- 👤 Naoki Mitsuishi
- 👤 Kiyoshi Matsubara
- 👤 Yoh Takamori
- 👤 Yoshiyuki Ozawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:53
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433; G11C16/22; G11C16/26
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
233 words
A single-chip microcomputer having a non-volatile memory and a central processing unit coupled to the non-volatile memory and to a random access memory, the non-volatile memory comprising: a memory array comprising a first group of non-volatile memory cells and a second group of non-volatile memory cells; electrical erasure means for executing an erasure operation on said memory array; selecting means, coupled to said memory array, for selecting a non-volatile memory cell from said memory array; designating means, coupled to the electrical erasure means, for designating whether the selected non-volatile memory cell is in the first group of non-volatile memory cells or in the second group of non-volatile memory cells; control register means, coupled to the electrical erasure means, for controlling the erasure operation of the electrical erasure means on said memory array including a first control bit means, the firsts control bit means having a first state for inhibiting the eraser operation of the electrical erasure means on the memory array and a second state for enabling the erasure operation of the electrical erasure means on the memory array; and, erase inhibit override means for inhibiting the erasure operation of the electrical erasure means on the second group of non-volatile memory cells regardless of the second state of the first control bit means when the designating means designates that the selected non-volatile memory cell is in the second group of non-volatile memory cells.
Claim 2
Dependent Claim
233 words
A single-chip microcomputer having a non-volatile memory and a central processing unit coupled to the non-volatile memory and to a random access memory, the non-volatile memory comprising: a memory array comprising a first group of non-volatile memory cells and a second group of non-volatile memory cells; electrical erasure means for executing an erasure operation on said memory array; selecting means, coupled to said memory array, for selecting a non-volatile memory cell from said memory array; designating means, coupled to the electrical erasure means, for designating whether the selected non-volatile memory cell is in the first group of non-volatile memory cells or in the second group of non-volatile memory cells; control register means, coupled to the electrical erasure means, for controlling the erasure operation of the electrical erasure means on said memory array including a first control bit means, the firsts control bit means having a first state for inhibiting the eraser operation of the electrical erasure means on the memory array and a second state for enabling the erasure operation of the electrical erasure means on the memory array; and, erase inhibit override means for inhibiting the erasure operation of the electrical erasure means on the second group of non-volatile memory cells regardless of the second state of the first control bit means when the designating means designates that the selected non-volatile memory cell is in the second group of non-volatile memory cells.
Claim 3
Dependent Claim
34 words
The single-chip microcomputer according to claim 1, further comprising: an interface circuit coupled to the central processing unit; and, an external access terminal means, coupled to the non-volatile memory, for accessing the non-volatile memory.
Claim 4
Dependent Claim
45 words
The single-chip microcomputer according to claim 2, wherein the interface circuit comprises communication means for sending data to and receiving data from a device external to the single-chip microcomputer, and wherein the single-chip microcomputer further includes a read only memory means for storing a program.
Claim 5
Dependent Claim
62 words
The single-chip microcomputer according to claim 2, further comprising: an external control terminal means for receiving a control signal; and, mode setting means, coupled to the external control terminal, for delivering a mode signal representative of whether said non-volatile memory is accessed by the central processing unit or accessed externally via said eternal access terminal means based on the control signal received.
Claim 6
Dependent Claim
104 words
The single-chip microcomputer according to claim 1, wherein the non-volatile memory further comprises writing means for executing a writing operation to said memory array, and wherein the control register means further comprises a second control bit means for controlling the writing operation of the writing means to said memory array, the second control bit means having a first state for inhibiting the writing operation of the writing means to said memory array, and a second state for enabling the writing operation of the writing means to said memory array, the states of said second control bit means being determined by said central processing unit.
Claim 7
Dependent Claim
27 words
The single-chip microcomputer according to claim 5, wherein said central processing unit comprises means for determining the first and second states of said second control bit means.
Claim 8
Dependent Claim
27 words
The single-chip microcomputer according to claim 1, wherein the central processing unit comprises means for determining said first and second states of the first control bit means.
Claim 9
Dependent Claim
28 words
The single-chip microcomputer according to claim 1, wherein said non-volatile memory comprises a plurality of non-volatile memory cells, each cell being an electrically erasable and programmable memory element.
Claim 10
Dependent Claim
238 words
An integrated circuit card comprising a single-chip microcomputer having a non-volatile memory and a central processing unit coupled to the non-volatile memory and to a random access memory, the non-volatile memory comprising: a memory array comprising a first group of non-volatile memory cells and a second group of non-volatile memory cells; electrical erasure means for executing an erasure operation on said memory array; selecting means, coupled to said memory array, for selecting a non-volatile memory cell from said memory array; designating means, coupled to the electrical erasure means, for designating whether the selected non-volatile memory cell is in the first group of non-volatile memory cells or in the second group of non-volatile memory cells; control register means, coupled to the electrical erasure means, for controlling the erasure operation of the electrical erasure means on said memory array including a first control bit means, the firsts control bit means having a first state for inhibiting the eraser operation of the electrical erasure means on the memory array and a second state for enabling the erasure operation of the electrical erasure means on the memory array; and, erase inhibit override means for inhibiting the erasure operation of the electrical erasure means on the second group of non-volatile memory cells regardless of the second state of the first control bit means when the designating means designates that the selected non-volatile memory cell is in the second group of non-volatile memory cells.
Claim 11
Dependent Claim
238 words
An integrated circuit card comprising a single-chip microcomputer having a non-volatile memory and a central processing unit coupled to the non-volatile memory and to a random access memory, the non-volatile memory comprising: a memory array comprising a first group of non-volatile memory cells and a second group of non-volatile memory cells; electrical erasure means for executing an erasure operation on said memory array; selecting means, coupled to said memory array, for selecting a non-volatile memory cell from said memory array; designating means, coupled to the electrical erasure means, for designating whether the selected non-volatile memory cell is in the first group of non-volatile memory cells or in the second group of non-volatile memory cells; control register means, coupled to the electrical erasure means, for controlling the erasure operation of the electrical erasure means on said memory array including a first control bit means, the firsts control bit means having a first state for inhibiting the eraser operation of the electrical erasure means on the memory array and a second state for enabling the erasure operation of the electrical erasure means on the memory array; and, erase inhibit override means for inhibiting the erasure operation of the electrical erasure means on the second group of non-volatile memory cells regardless of the second state of the first control bit means when the designating means designates that the selected non-volatile memory cell is in the second group of non-volatile memory cells.
Claim 12
Dependent Claim
90 words
The integrated circuit card according to claim 9, wherein the non-volatile memory further comprises writing means for executing a writing operation to said memory array, and wherein the control register means further comprises a second control bit means for controlling the writing operation of the writing means to said memory array, the second control bit means having a first state for inhibiting the writing operation of the writing means to said memory array, and a second state for enabling the writing operation of the writing means to said memory array.
Claim 13
Dependent Claim
28 words
The integrated circuit card according to claim 10, wherein said central processing unit comprises means for determining the first and second states of said first control bit means.
Claim 14
Dependent Claim
28 words
The integrated circuit card according to claim 11, wherein the central processing unit comprises means for determining the first and second states of said second control bit means.
Claim 15
Dependent Claim
28 words
The integrated circuit card according to claim 9, wherein the central processing unit comprises means for determining said first and second states of the first control bit means.
Claim 16
Dependent Claim
29 words
The integrated circuit card according to claim 9, wherein said non-volatile memory comprises a plurality of non-volatile memory cells, each cell being an electrically erasable and programmable memory element.
References Cited (Backward Citations)
US4130890A
Cited
US4447887A
Cited
US4408306A
Cited
US4506322A
Cited
US4482047A
Cited
US4521852A
Cited
US4829469A
Cited
JPS5971180A
Cited
JPS5998395A
Cited
US4686620A
Cited
US4698750A
Cited
US4744062A
Cited
US4821240A
Cited
US4752871A
Cited
US4802117A
Cited
US4931993A
Cited
US4849942A
Cited
US4860228A
Cited
US4931997A
Cited
US4926388A
Cited
US4975878A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-27 | 1995-07-29 | 1996-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-27 | 1999-07-29 | 2000-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-27 | 2003-07-29 | 2004-01-28 | $7700.00 | Window Closed / Lapsed |