Binary signal generating circuit with parallel sample and hold circuits and common sampling switch

Claim 2

A sample and hold circuit device including a plurality of sample and hold circuits which are parallel-connected, wherein: each of said sample and hold circuits has an input end connected to the input ends of the other sample and hold circuits, and an internal node for receiving an analog signal fed in through said input end, said device comprising an analog signal input terminal for inputting the analog signal to be sampled and held in said sample and hold circuits, a sampling switch interposed between said connected input ends of the sample and hold circuits and said analog signal input terminal and adapted to be turned on thereby to introduce said analog signal into the sample and hold circuits and turned off thereby to cause the analog signal fed in at that time to be sampled and held in the sample and hold circuits, and a plurality of averaging switches interposed between said internal nodes and said interconnected input ends of said sample and hold circuits and adapted to be turned on thereby to interconnect said internal nodes and average the analog signal values sampled and held in the sample and hold circuits and turned off thereby to electrically disconnect said internal nodes of said sample and hold circuits from each other.

Claim 3

A sample and hold circuit device as set forth in claim 1, wherein: for said analog signal input terminal, there are provided a plurality of sets of said sample and hold circuits groups having their input ends interconnected, said sampling switch is provided separately from the sets of said sample and hold circuits groups.

Claim 4

A binary signal generating circuit for generating a binary signal corresponding to an input analog signal, comprising: a plurality of sample and hold circuits having their input ends interconnected, said sample and hold circuits having internal nodes for receiving analog signals fed from said input ends, an analog signal input terminal for inputting an analog signal to be sampled and held in the sample and hold circuits, a plurality of reference voltage input terminals for inputting reference voltages to be imparted to said sample and hold circuits, a sampling switch interposed between said interconnected input ends of said sample and hold circuits and said analog signal input terminal and adapted to be turned on thereby to introduce said analog signal into said sample and hold circuits and turned off thereby to cause the analog signal fed in at that time to be sampled and held in the sample and hold circuits, a plurality of averaging switches interposed between said internal nodes and said interconnected input ends of said sample and hold circuits and adapted to be turned on thereby to interconnect said internal nodes and average the analog signal values sampled and held in the sample and hold circuits and turned off thereby to electrically disconnect said internal nodes of said sample and hold circuits, a plurality of reference voltage applying switches interposed between said internal nodes of said sample and hold circuits and the corresponding reference voltage input terminal and adapted to be turned on thereby to apply reference voltages from the reference voltage input terminals to the internal nodes and turned off thereby to prevent the reference voltages from being applied to the internal nodes, and a plurality of comparing means associated with said sample and hold circuits and adapted to compare the analog signal values sampled and held in the sample and hold circuits with the corresponding reference voltages and generate a binary signal having the corresponding size.

Claim 5

A binary signal generating circuit for generating a binary signal corresponding to an input analog signal, comprising: a plurality of sample and hold circuits having their input ends interconnected, said sample and hold circuits having internal nodes for receiving analog signals fed from said input ends, an analog signal input terminal for inputting an analog signal to be sampled and held in the sample and hold circuits, a plurality of reference voltage input terminals for inputting reference voltages to be imparted to said sample and hold circuits, a sampling switch interposed between said interconnected input ends of said sample and hold circuits and said analog signal input terminal and adapted to be turned on thereby to introduce said analog signal into said sample and hold circuits and turned off thereby to cause the analog signal fed in at that time to be sampled and held in the sample and hold circuits, a plurality of averaging switches interposed between said internal nodes and said interconnected input ends of said sample and hold circuits and adapted to be turned on thereby to interconnect said internal nodes and average the analog signal values sampled and held in the sample and hold circuits and turned off thereby to electrically disconnect said internal nodes of said sample and hold circuits, a plurality of reference voltage applying switches interposed between said internal nodes of said sample and hold circuits and the corresponding reference voltage input terminal and adapted to be turned on thereby to apply reference voltages from the reference voltage input terminals to the internal nodes and turned off thereby to prevent the reference voltages from being applied to the internal nodes, and a plurality of comparing means associated with said sample and hold circuits and adapted to compare the analog signal values sampled and held in the sample and hold circuits with the corresponding reference voltages and generate a binary signal having the corresponding size.

Claim 6

An A/D converter for converting an input analog signal to a digital signal, comprising: an analog signal input terminal for inputting said analog signal. a plurality of sample and hold circuits for sampling and holding the analog signal inputted from the analog signal input terminal, reference voltage generating means for generating reference voltages to be imparted to said sample and hold circuits, a plurality of comparing means associated with said sample and hold circuits and adapted to compare the analog signal values sampled and held in the sample and hold circuits with the corresponding reference voltages imparted from said reference voltage generating means and generate a binary signal having the corresponding size, and encoding means for converting the binary signal outputs from said comparing means into digital signals corresponding to said inputted analog signals, said sample and hold circuits having their input ends interconnected, and internal nodes for receiving analog signals introduced from said input ends, a sampling switch interposed between the interconnected input ends of said sample and hold circuits and said analog signal input terminal and adapted to be turned on thereby to introduce said analog signal into said sample and hold circuits and turned off thereby to cause the analog signals introduced at that time to be sampled and held in the sample and hold circuits, and a plurality of averaging switches interposed between the internal nodes and the interconnected input ends of said sample and hold circuits and adapted to be turned on thereby to connect said internal nodes to each other and average the analog signal values sampled and held in the sample and hold circuits and turned off thereby to electrically disconnect said internal nodes of said sample and hold circuits from each other.

Claim 7

An A/D converter for converting an input analog signal to a digital signal, comprising: an analog signal input terminal for inputting said analog signal. a plurality of sample and hold circuits for sampling and holding the analog signal inputted from the analog signal input terminal, reference voltage generating means for generating reference voltages to be imparted to said sample and hold circuits, a plurality of comparing means associated with said sample and hold circuits and adapted to compare the analog signal values sampled and held in the sample and hold circuits with the corresponding reference voltages imparted from said reference voltage generating means and generate a binary signal having the corresponding size, and encoding means for converting the binary signal outputs from said comparing means into digital signals corresponding to said inputted analog signals, said sample and hold circuits having their input ends interconnected, and internal nodes for receiving analog signals introduced from said input ends, a sampling switch interposed between the interconnected input ends of said sample and hold circuits and said analog signal input terminal and adapted to be turned on thereby to introduce said analog signal into said sample and hold circuits and turned off thereby to cause the analog signals introduced at that time to be sampled and held in the sample and hold circuits, and a plurality of averaging switches interposed between the internal nodes and the interconnected input ends of said sample and hold circuits and adapted to be turned on thereby to connect said internal nodes to each other and average the analog signal values sampled and held in the sample and hold circuits and turned off thereby to electrically disconnect said internal nodes of said sample and hold circuits from each other.

Claim 8

An A/D converter as set forth in claim 4, including a plurality of reference voltage applying switches each associated with each sample and hold circuit and adapted to be turned on thereby to apply the corresponding reference voltage from said reference voltage generating circuit to said internal nodes and turned off thereby to prevent the corresponding reference voltage from being applied to said internal nodes.