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JPH0241028A Expired / Lapsed JP ⏱️ 0.0 years remaining

Analog/digital conversion circuit

Assignee: Sony Corp
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Filing: 1988-07-30
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Granted: —
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Expires: 2008-07-30
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Abstract

Abstract PURPOSE:To prevent an error of the result of comparison caused by the dispersion in the ON-resistance of each sampling switch circuit by applying on-control to each averaging switch circuit so as to apply averaging to a hold voltage subjected to sample and hold in each holding capacitor. CONSTITUTION:Sampling switch circuits SWF1-SWF15 are switched from OFF to ON in the timing at a point of time t10, and averaging switch circuits SWAU1- SWAU15 are switched from OFF to ON at a point of time t11 retarded by a prescribed time tau10. Then each circuit SWFn is switched from ON to OFF at a point of time t12, while each circuit SWAUn is switched from ON to OFF with a delay t13 from a point of time t12 by a prescribed time tau11. A voltage of an input video signal VDIN is held in holding capacitors CF1-CF15 and a holding voltage held in capacitors CF1-CF15 is averaged.

Inventors

  • 👤 Noriyuki Fukushima
  • 👤 範之 福島
  • 👤 Naoki Kumazawa
  • 👤 熊沢 直樹

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 20:19
CPC Classifications
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