US4903028A
Expired / Lapsed
US
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Analog-to-digital converter
Assignee: Sony Corp
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Filing: 1989-01-19
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Granted: 1990-02-20
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Expires: 2009-01-19
Abstract
Abstract An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits which has a plurality of resistors connected in a series circuit to a voltage source for establishing respective reference voltages, an upper bit encoder having a first input receiving the analog input voltage and second inputs connected to the series circuit at respective intervals defining groups of the resistor therebetween for generating the m upper bits and a switch control signal, each of the groups including a plurality of the resistors, a first lower bit encoder having a first input receiving the analog input voltage signal and second inputs for generating the n lower bits, a second lower bit encoder having a first input receiving the analog input voltage signal and second inputs for generating the n lower bits, a switch circuit associated with each of the groups of the resistors and responsive to the switch control signal for selectively connecting each of the second inputs of the first and second lower bit encoders to respective resistors in the associated group of the resistors, and a circuit for alernately combining the m upper bits with the n lower bits generated by the first and second lower bit encoders and for generating the digital output voltage signal.
Inventors
- 👤 Noriyuki Fukushima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:24
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/06; H03M1/0617; H03M1/0675; H03M1/069; C; C04; C04B; C04B35/00; C04B35/71; C04B35/78; C04B35/80; H03M1/14; H03M1/145; H03M1/146; H03M1/147; H03M1/148
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
225 words
An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits, comprising: a plurality of resistor means connected in a series circuit to a voltage source for establishing respective reference voltages; upper bit encoder means having a first input receiving said analog input voltage and second inputs connected to said series circuit at respective intervals defining groups of said resistor means therebetween for generating said m upper bits and a switch control signal, each of said groups including a plurality of said resistor means; first lower bit encoder means having a first input receiving said analog input voltage signal and second inputs for generating said n lower bits; second lower bit encoder means having a first input receiving said analog input voltage signal and second inputs for generating said n lower bits; switch means associated with each of said groups of said resistor means and responsive to said switch control signal for selectively connecting each of said second inputs of said first and second lower bit encoder means to respective resistor means in said associated group of said resistor means, and means for alternately combining said m upper bits with said n lower bits generated by said first and second lower bit encoder means, and for generating said digital output voltage signal.
Claim 2
Dependent Claim
225 words
An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits, comprising: a plurality of resistor means connected in a series circuit to a voltage source for establishing respective reference voltages; upper bit encoder means having a first input receiving said analog input voltage and second inputs connected to said series circuit at respective intervals defining groups of said resistor means therebetween for generating said m upper bits and a switch control signal, each of said groups including a plurality of said resistor means; first lower bit encoder means having a first input receiving said analog input voltage signal and second inputs for generating said n lower bits; second lower bit encoder means having a first input receiving said analog input voltage signal and second inputs for generating said n lower bits; switch means associated with each of said groups of said resistor means and responsive to said switch control signal for selectively connecting each of said second inputs of said first and second lower bit encoder means to respective resistor means in said associated group of said resistor means, and means for alternately combining said m upper bits with said n lower bits generated by said first and second lower bit encoder means, and for generating said digital output voltage signal.
Claim 3
Dependent Claim
27 words
An analog-to-digital converter according to claim 1, wherein said resistor means are arranged in a plurality of rows, each of said groups constituting one of said rows.
Claim 4
Dependent Claim
41 words
An analog-to-digital converter according to claim 1, wherein said upper bit encoder means comprises at least 2 m -1 upper bit comparators and said first and second lower bit encoder means respectively comprise at least 2 n -1 lower bit comparators.
Claim 5
Dependent Claim
46 words
An analog-to-digital converter according to claim 1, wherein said resistor means are arranged in a zigzag pattern, said upper bit encoder means generates an inverting control signal and said converter further comprises means for inverting said n lower bits in response to said inverting control signal.
Claim 6
Dependent Claim
248 words
An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits, comprising: a plurality of resistor means connected in a series circuit to a voltage source for establishing respective reference voltages; upper bit encoder means having a first input receiving said analog input voltage and second inputs connected to said series circuit at respective intervals defining groups of said resistor means therebetween for generating said m upper bits and a switch control signal, each of said groups including a plurality of said resistor means; lower bit encoder means having a first input receiving said analog input voltage signal, second inputs and third inputs for generating said n lower bits; switch means associated with each of said groups of said resistor means and responsive to said switch control signal for selectively connecting each of said second inputs of said lower bit encoder means to respective resistor means in said associated group of said resistor means and for selectively connecting each of said third inputs of said lower bit encoder means to a predetermined number of said resistor means adjoining to and outside said associated group of said resistor means; and means responsive to an output signal from said lower bit encoder means for adding 1 to or subtracting 1 from said m upper bits when said analog input voltage signal corresponds to said reference voltages supplied to said third inputs of said lower bit encoder means.
Claim 7
Dependent Claim
248 words
An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits, comprising: a plurality of resistor means connected in a series circuit to a voltage source for establishing respective reference voltages; upper bit encoder means having a first input receiving said analog input voltage and second inputs connected to said series circuit at respective intervals defining groups of said resistor means therebetween for generating said m upper bits and a switch control signal, each of said groups including a plurality of said resistor means; lower bit encoder means having a first input receiving said analog input voltage signal, second inputs and third inputs for generating said n lower bits; switch means associated with each of said groups of said resistor means and responsive to said switch control signal for selectively connecting each of said second inputs of said lower bit encoder means to respective resistor means in said associated group of said resistor means and for selectively connecting each of said third inputs of said lower bit encoder means to a predetermined number of said resistor means adjoining to and outside said associated group of said resistor means; and means responsive to an output signal from said lower bit encoder means for adding 1 to or subtracting 1 from said m upper bits when said analog input voltage signal corresponds to said reference voltages supplied to said third inputs of said lower bit encoder means.
Claim 8
Dependent Claim
27 words
An analog-to-digital converter according to claim 5, wherein said resistor means are arranged in a plurality of rows, each of said groups constituting one of said rows.
Claim 9
Dependent Claim
38 words
An analog-to-digital converter according to claim 5, wherein said upper bit encoder means comprises at least 2 m -1 upper bit comparators and said lower bit encoder means respectively comprises at least 2 n -1 lower bit comparators.
Claim 10
Dependent Claim
46 words
An analog-to-digital converter according to claim 5, wherein said resistor means are arranged in a zigzag pattern, said upper bit encoder means generates an inverting control signal, and said converter further comprises means for inverting said n lower bits in response to said inverting control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |