US5075574A
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US
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Differential cascode current switch (dccs) logic circuit family with input diodes
Assignee: International Business Machines Corp
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Filing: 1990-06-20
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Granted: 1991-12-24
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Expires: 2010-06-20
Abstract
Abstract The present logic circuit family is derived from the conventional DCCS logic circuit family. The logic circuit shown in the attached drawing is a six-input AND/NAND. It includes: a logic tree (41) comprised of bottom, middle, and top stages (44, 45, 46) cascoded and dotted at the tree output nodes (OUT, OUT) to perform a determined logic function (F, F). The top stage (46) includes a current switch (49) formed by a pair of input transistors (TX431, TX432) connected in a differential amplifier configuration. The base of one input transistor (TX431) on the left side of the tree is connected to the output of an AND gate, which consists of input diodes (D431, D432, . . . ) and resistor (RD41). True (IN PHASE) logic input signals (Z41, Z42, . . . ) are ANDed in this AND gate and a first elementary output signal, is available at the common emitter node (CN43) of the said differential pair. On the right side, additional inpout transistors (TX433, . . . ) are paralleled with the other input transistor (TX432) of the differential pair, so that the complementary (OUT OF PHASE) input signals (Z41, Z42, . . . ) that drive the transistors, are ORed to deliver a second elementary output signal, complementary to said first elementary output signal, on said common emitter node (CN43). Same principle applies at the first and second levels to build the bottom (44) and middle (45) stages. The present invention allows to increase the number of logical inputs to be applied to a DCCS logic circuit, and in turn, the number of logic functions performed in the logic DCCS tree. As a result, an extended library of DCCS logic circuits may be obtained.
Inventors
- 👤 Gerard Boudon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 01:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1738
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
253 words
A logic circuit of the DCCS type including: a logic tree (41) formed by a plurality of stages (44, 45, 46) cascoded and dotted to perform a determined logic function F between IN PHASE and OUT OF PHASE input signals (Z41,...; Z41,...) and its complement F, at the tree output nodes (OUT, OUT) in the top stage (46); wherein each stage (e.g., 46) of the current switch type basically consists of a pair of input transistors (e.g., TX432, TX431) connected in a differential amplifier configuration, forming two independent branches and whose emitters are tied together to form a common emitter node (e.g., CN43); a pair of load resistors (RCT4, RCC4) to connect said output nodes (OUT, OUT) to a first supply voltage (VPP); a current source connected to a second supply voltage supplying a constant current (IO) to the common emitter node (CN41) of the bottom stage (44) of said logic tree (41); CHARACTERIZED IN THAT at least one stage (e.g., 46) further includes: first logic input means connected to the base of one input transistor driven by a first combination of said IN PHASE and OUT OF PHASE input signals to deliver a first elementary logic function on the common node of said stage; and, second logic input means connected to at least one electrode of the other input transistor driven by a second combination of said input signals, to deliver a second elementary logic function, complementary to said first function, on said common emitter node where these functions are summed up.
Claim 2
Dependent Claim
253 words
A logic circuit of the DCCS type including: a logic tree (41) formed by a plurality of stages (44, 45, 46) cascoded and dotted to perform a determined logic function F between IN PHASE and OUT OF PHASE input signals (Z41,...; Z41,...) and its complement F, at the tree output nodes (OUT, OUT) in the top stage (46); wherein each stage (e.g., 46) of the current switch type basically consists of a pair of input transistors (e.g., TX432, TX431) connected in a differential amplifier configuration, forming two independent branches and whose emitters are tied together to form a common emitter node (e.g., CN43); a pair of load resistors (RCT4, RCC4) to connect said output nodes (OUT, OUT) to a first supply voltage (VPP); a current source connected to a second supply voltage supplying a constant current (IO) to the common emitter node (CN41) of the bottom stage (44) of said logic tree (41); CHARACTERIZED IN THAT at least one stage (e.g., 46) further includes: first logic input means connected to the base of one input transistor driven by a first combination of said IN PHASE and OUT OF PHASE input signals to deliver a first elementary logic function on the common node of said stage; and, second logic input means connected to at least one electrode of the other input transistor driven by a second combination of said input signals, to deliver a second elementary logic function, complementary to said first function, on said common emitter node where these functions are summed up.
Claim 3
Dependent Claim
47 words
The logic circuit of claim 1 wherein said first input means consists of an AND gate (D431, D432, R41) whose output is connected to the base of said one input transistor (TX431), and which performs an AND function between the IN PHASE input signals (Z41, Z42, ...).
Claim 4
Dependent Claim
70 words
The logic circuit of claim 2 wherein said second input means consists of a plurality of additional input transistors (TX433, ...) connected in parallel with said other input transistor (TX432); and wherein the base of said other input transistor is driven by one OUT OF PHASE input signal (Z41), and the bases of said additional input transistors are driven by the remaining of said OUT OF PHASE input signals(Z42, ...).
Claim 5
Dependent Claim
176 words
The logic circuit of claim 1 wherein said first input means consists of a two-input AND gate (D631, D632, RD61) whose output is connected to the base of said one input transistor (TX631); said two-input AND gate being driven in turn by the signals supplied by two two-input OR gates (TX61, TX62; TX63, TX64); the first OR gate being driven by a couple of IN PHASE input signals (Z61, Z62) and the second OR gate being driven by the corresponding couple of OUT OF PHASE input signals (Z61, Z62); and , wherein said second input means consists of a two-input AND gate (D633, D634, RD62) whose output is connected to the base of said other input transistor (TX632); said two-input AND gate being driven in turn by the signals supplied by two two-input OR gates (TX65, TX66; TX67, TX68); the first OR gate being driven by a couple of mixed IN PHASE and OUT OF PHASE input signals (Z61, Z62), and the second OR gate being driven by the couple of complementary input signals (Z61, Z62).
Claim 6
Dependent Claim
24 words
The logic circuit of claim 2 further comprising a pair of differential transistors connected to each transistors and respectively connected to said output nodes.
Claim 7
Dependent Claim
26 words
The logic circuit of claim 2 wherein level shifter means (D41, ...) is inserted the said base of second input transistor and said additional input transistors.
Claim 8
Dependent Claim
31 words
The logic circuit of claim 3 wherein a resistor (R42, R43, is connected to the base of said second transistor and to each of the bases of said additional input transistors.
Claim 9
Dependent Claim
26 words
The logic circuit of claim 2 wherein said AND gate consists of diodes (D431, ...) whose anodes are connected together and loaded by a resistor (RD41).
Claim 10
Dependent Claim
16 words
The logic circuit of claim 1 wherein first supply voltage (VPP) is lower than 3.4 V.
Claim 11
Dependent Claim
30 words
The logic circuit of claim 1 further including: at least one translator circuit (42) including an emitter-follower transistor (TY2) which is driven by the potential at said tree output node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-23 | 1995-06-24 | 1995-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-23 | 1999-06-24 | 1999-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-23 | 2003-06-24 | 2003-12-24 | $7700.00 | Window Closed / Lapsed |