Patent US5073516A successfully refreshed from Google Patents.
US5073516A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Selective epitaxial growth process flow for semiconductor technologies
Assignee: Texas Instruments Inc
•
Filing: 1991-02-28
•
Granted: 1991-12-17
•
Expires: 2011-02-28
Abstract
Abstract This is a method of fabricating a high-performance semiconductor device. The method comprises: forming a first insulating structure, preferably a layer of silicon nitride (e.g. region 24 in FIG. 2) on a layer of thermally grown oxide (e.g. region 22), on a substrate (e.g. region 20), preferably silicon; patterning and anisotropically etching the first insulating structure to expose a portion of the substrate and sidewalls of the first insulating structure; forming a second insulating structure, preferably a layer of oxide (e.g. region 28 in FIG. 3) on a layer of nitride (the bottom second insulating layer is preferably an etch-stop layer with respect to the removal of the top second insulating layer) (e.g. region 26 in FIG. 3), on the patterned first insulating structure, along the sidewalls of the first insulating structure, and on the exposed semiconductor substrate; anisotropically removing portions of the second insulating structure leaving a sidewall region of the second insulating structure (e.g. regions 30 and 32 in FIG. 4) along the sidewall of the first insulating structure and a region of the second insulating structure on a portion of the exposed substrate, and exposing a portion of the exposed substrate; forming a region of semiconducting material (e.g. regions 36 and 34, respectively, in FIG. 5), preferably a selectively grown semiconducting layer (preferably in-situ doped epitaxial silicon), encompassed by the second insulating structure and the exposed region of the substrate; sequentially and selectively etching the second insulating sidewall region to substantially expose the sidewalls of the selectively grown semiconducting region and top of the semiconducting region; and forming a third insulating layer (e.g. region 40 in FIG. 8 and region b 46 in FIG. 11), preferably a thermally grown oxide layer or a low-temperature plasma oxidation layer, on the exposed semiconducting region and on the exposed sidewalls of the semiconducting region.
Inventors
- 👤 Mehrdad M. Moslehi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:08
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/27; H10P14/271; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/018; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/05; Y10S148/097
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
190 words
A method of fabricating a semiconductor device, wherein said method comprises: a. forming a first insulating structure on a substrate; b. patterning and etching said first insulating layer to expose a portion of said substrate and sidewalls of said first insulating structure; c. forming a second insulating structure comprising a top insulating layer and a bottom insulating layer on said patterned first insulating structure, along said sidewalls of said first insulating structure, and on said exposed substrate; d. anisotropically removing portions of said second insulating structure leaving a sidewall region of said second insulating material along said sidewall of said first insulating structure and a region of said second insulating structure on a portion of said exposed substrate, and exposing a portion of said exposed substrate; e. selectively forming a region of semiconducting material encompassed by said second insulating structure and said exposed region of said substrate; f. etching said second insulating sidewall region to substantially expose said sidewalls of said semiconducting region and top of said semiconducting region; and g. forming a third insulating layer on said exposed semiconducting region and on said exposed sidewalls of said semiconducting region.
Claim 2
Independent Claim
190 words
A method of fabricating a semiconductor device, wherein said method comprises: a. forming a first insulating structure on a substrate; b. patterning and etching said first insulating layer to expose a portion of said substrate and sidewalls of said first insulating structure; c. forming a second insulating structure comprising a top insulating layer and a bottom insulating layer on said patterned first insulating structure, along said sidewalls of said first insulating structure, and on said exposed substrate; d. anisotropically removing portions of said second insulating structure leaving a sidewall region of said second insulating material along said sidewall of said first insulating structure and a region of said second insulating structure on a portion of said exposed substrate, and exposing a portion of said exposed substrate; e. selectively forming a region of semiconducting material encompassed by said second insulating structure and said exposed region of said substrate; f. etching said second insulating sidewall region to substantially expose said sidewalls of said semiconducting region and top of said semiconducting region; and g. forming a third insulating layer on said exposed semiconducting region and on said exposed sidewalls of said semiconducting region.
Claim 3
Dependent Claim
76 words
The method of claim 1, wherein said top second insulating sidewall region and said bottom second insulating sidewall region are selectively and sequentially removed (with respect to said semiconducting region, said substrate, and said patterned first insulating structure) to expose said sidewall of said patterned first insulating structure, a portion of said exposed substrate between said sidewall of said patterned first insulating structure and sidewalls of said semiconducting region, and said sidewalls of said semiconducting region.
Claim 4
Dependent Claim
32 words
The method of claim 2, wherein said third insulating layer is formed on said exposed portion of said exposed substrate, on said sidewalls of said semiconducting region, and on said semiconducting region.
Claim 5
Dependent Claim
31 words
The method of claim 3, wherein a non conductive material is utilized to fill the region encompassed by said sidewalls of said patterned first insulating layer and said third insulating layer.
Claim 6
Dependent Claim
17 words
The method of claim 4, wherein exposed said third insulating layer on said semiconducting region is removed.
Claim 7
Dependent Claim
34 words
The method of claim 4, wherein said third insulating layer on said semiconducting region and abutting said non conducting material, and excess said non conductive material are removed in the same etch process step.
Claim 8
Dependent Claim
49 words
The method of claim 1, wherein said top second insulating sidewall region is selectively removed (with respect to said bottom second insulating sidewall region, said patterned first insulating region, and said semiconducting region) to substantially expose said sidewalls of said semiconducting region and said bottom second insulating sidewall region.
Claim 9
Dependent Claim
28 words
The method of claim 7, wherein said third insulating material is formed on said exposed regions of said sidewalls of said semiconducting region and on said semiconducting region.
Claim 10
Dependent Claim
65 words
The method of claim 8, wherein said bottom second insulating sidewall region is removed to expose said sidewall of said patterned first insulating layer, a portion of said exposed substrate between said sidewall of said patterned first insulating layer and said sidewall of said semiconducting region, and a portion of said sidewall of said semiconducting region between said exposed substrate and said third insulating layer.
Claim 11
Dependent Claim
50 words
The method of claim 9, wherein a plug is formed in the region encompassed by said exposed said walls of said patterned first insulating layer, said exposed portion of said exposed substrate, said exposed portion of said sidewall of said semiconducting region, and a portion of said third insulating material.
Claim 12
Dependent Claim
21 words
The method of claim 1, wherein said semiconducting region is comprised of a top semiconducting region and a bottom semiconducting region.
Claim 13
Dependent Claim
27 words
The method of claim 1, wherein said bottom second insulating layer is an etch stop layer with respect to the removal of said top second insulating layer.
Claim 14
Dependent Claim
22 words
The method of claim 1, wherein said first insulating structure is comprised of a top insulating layer and a bottom insulating layer.
Claim 15
Dependent Claim
23 words
The method of claim 13, wherein said bottom second insulating layer is comprised of the same material as said top first insulating layer.
Claim 16
Dependent Claim
23 words
The method of claim 1, wherein said third insulating layer is selected from the group consisting of: oxides, nitrides, or any combination thereof.
Claim 17
Dependent Claim
32 words
The method of claim 1, where said forming of said third insulating layer is selected from the group consisting of: thermal oxidation, thermal nitridation, oxynitridation, low-temperature plasma oxidation, or any combination thereof.
Claim 18
Dependent Claim
24 words
The method of claim 13, wherein said bottom first insulating layer is selected from the group consisting of nitrides, oxides, or any combination thereof.
Claim 19
Dependent Claim
32 words
The method of claim 1, wherein said providing of said bottom first insulating material is selected from the group consisting of thermal oxidation, chemical vapor deposition, physical-vapor deposition, or any combination thereof.
Claim 20
Dependent Claim
24 words
The method of claim 12, wherein said top first insulating layer is selected from the group consisting of nitrides, oxides, or any combination thereof.
Claim 21
Dependent Claim
24 words
The method of claim 1, wherein said bottom second insulating material is selected from the group consisting of nitrides, oxides, or any combination thereof.
Claim 22
Dependent Claim
24 words
The method of claim 1, wherein said top second insulating material is selected from the group consisting of nitrides, oxides, or any combination thereof.
Claim 23
Dependent Claim
27 words
The method of claim 3, wherein said non-conducting material is selected from the group consisting of nitrides, oxides, undoped polysilicon, undoped amorphous silicon, or any combination thereof.
Claim 24
Dependent Claim
14 words
The method of claim 1, wherein said semiconducting region is in situ doped silicon.
Claim 25
Dependent Claim
16 words
The method of claim 1, wherein said forming of said semiconducting region is selective epitaxial growth.
Claim 26
Dependent Claim
14 words
The method of claim 1, wherein said semiconducting region comprises doped active device junctions.
Claim 27
Dependent Claim
30 words
The method of claim 10, wherein said plug is selected form the group consisting of: in-situ doped polycrystalline silicon, undoped silicon, tungsten, amorphous silicon, epitaxial silicon, or any combination thereof.
Claim 28
Dependent Claim
16 words
The method of claim 10, wherein said formation of said plug is selectively growing said plug.
Claim 29
Dependent Claim
12 words
The method of claim 1, wherein said substrate is single crystal silicon.
Claim 30
Dependent Claim
29 words
The method of claim 8, wherein a layer of fourth insulating material is provided in the region encompassed by said bottom second insulating layer and said third insulating layer.
Claim 31
Dependent Claim
25 words
The method of claim 29, wherein said fourth insulating material is selected from the group consisting of undoped silicon, nitrides, oxides, or any combination thereof.
Claim 32
Independent Claim
292 words
A method of fabricating a semiconductor device, said method comprising: a. providing a first oxide layer on a semiconductor substrate; b. depositing a first nitride layer; c. patterning and etching said first oxide layer and said first nitride layer to provide a region in which the substrate and a wall of said first oxide and first nitride layers are exposed; d. depositing a second nitride layer over said patterned first nitride layer, over said exposed substrate, and on said wall of said first oxide and first nitride layers; e. depositing a second oxide layer on said second nitride layer; f. anisotropically etching said second oxide and second nitride layers to substantially remove all of said layers over said patterned first nitride layer and said exposed substrate leaving a region of substantially unetched said second oxide and second nitride layers along said wall of said first oxide and first nitride layers; g. providing a selectively grown silicon region on said exposed substrate; h. selectively etching said second oxide layer to expose sidewalls of said selectively grown silicon region and sidewalls of said second nitride layer; i. selectively etching said second nitride layer and said first nitride layer to expose top and sidewalls of said patterned first oxide layer, a region of said exposed substrate between said selectively grown silicon region and said sidewall of said patterned first oxide layer, and sidewalls of said selectively grown silicon region; j. providing a third oxide layer on said selectively grown silicon region, on said exposed region of said exposed substrate, and on said sidewalls of said selectively grown silicon region; and k. providing an undoped polycrystalline silicon to substantially fill the region between said sidewall of said patterned first oxide layer and said third oxide layer.
Claim 33
Independent Claim
292 words
A method of fabricating a semiconductor device, said method comprising: a. providing a first oxide layer on a semiconductor substrate; b. depositing a first nitride layer; c. patterning and etching said first oxide layer and said first nitride layer to provide a region in which the substrate and a wall of said first oxide and first nitride layers are exposed; d. depositing a second nitride layer over said patterned first nitride layer, over said exposed substrate, and on said wall of said first oxide and first nitride layers; e. depositing a second oxide layer on said second nitride layer; f. anisotropically etching said second oxide and second nitride layers to substantially remove all of said layers over said patterned first nitride layer and said exposed substrate leaving a region of substantially unetched said second oxide and second nitride layers along said wall of said first oxide and first nitride layers; g. providing a selectively grown silicon region on said exposed substrate; h. selectively etching said second oxide layer to expose sidewalls of said selectively grown silicon region and sidewalls of said second nitride layer; i. selectively etching said second nitride layer and said first nitride layer to expose top and sidewalls of said patterned first oxide layer, a region of said exposed substrate between said selectively grown silicon region and said sidewall of said patterned first oxide layer, and sidewalls of said selectively grown silicon region; j. providing a third oxide layer on said selectively grown silicon region, on said exposed region of said exposed substrate, and on said sidewalls of said selectively grown silicon region; and k. providing an undoped polycrystalline silicon to substantially fill the region between said sidewall of said patterned first oxide layer and said third oxide layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |