Abstract This invention relates to a method of manufacturing a DRAM cell which has a stacked capacitor and forming drain and source polycrystalline silicon regions on surface of a semiconductor substrate. The invention is directed to: a first step for forming a field oxide film and channel stopper as well as a polycrystalline silicon oxide film doped with impurities; a second step for dividing said silicon into a drain and source polycrystalline silicon region and forming a gate oxide film between the two silicon regions simultaneously with the drain and source diffusion regions and a gate electrode on the gate nitride film; a third step for forming an insulating film on the upper surface of the nitride film and a window on the source polycrystalline silicon region, a storage poly contacting with the same through the window; a fourth step for forming a dielectric layer and a plate poly of the stacked capacitor; and a fifth step forming another insulating film thereon and forming a window on the drain polycrystalline silicon region and also forming a bit line contacting with the exposed drain polycrystalline silicon region through that window. This invention can prevent the generation of leakage current resulting from the damage caused by the drain and source diffusion polycrystalline silicon regions when an etching process is used for the formation of the storage poly and the bit line.
A method of manufacturing a DRAM cell having a stacked capacitor, comprising the steps of: forming first and second field oxide films on a semiconductor substrate of a first conductive type, forming a channel stopper of said first conductive type on the low portion of the first field oxide film, and forming a polycrystalline silicon doped with impurities of a second conductive type and a nitride film in order; dividing said polycrystalline silicon into drain and source polycrystalline silicon regions, and simultaneously forming a gate oxide film on the surface of said substrate between said drain and source polycrystalline silicon regions, and drain and source diffusion regions of the second conductive type and forming a gate electrode on a top portion of the gate oxide film; forming a first insulating film on an upper surface of said nitride film and the gate electrode, and forming a window at a predetermined portion of the top portion of said source polycrystalline silicon and a storage poly contacting with the source polycrystalline silicon exposed through said window; forming a dielectric layer which becomes a dielectric substance of the stacked capacitor and a plate poly on the top portion of said storage poly; and forming a second insulating film on the top portion of said first insulating film and the plate poly and forming a window at a predetermined portion of the top portion of said drain polycrystalline silicon region, and a bit line contacting with the drain polycrystalline silicon region exposed through said window, wherein said polycrystalline silicon doped with impurities of the second conductive type and said nitride film are deposited over an entire area of the semiconductor substrate and the first and second field oxide films, said storage poly is contacted with the source polycrystalline silicon superposed on the first field oxide film, and said bit line is contacted with the drain polycrystalline silicon superposed on the second field oxide film.
Claim 2
Independent Claim
320 words
A method of manufacturing a DRAM cell having a stacked capacitor, comprising the steps of: forming first and second field oxide films on a semiconductor substrate of a first conductive type, forming a channel stopper of said first conductive type on the low portion of the first field oxide film, and forming a polycrystalline silicon doped with impurities of a second conductive type and a nitride film in order; dividing said polycrystalline silicon into drain and source polycrystalline silicon regions, and simultaneously forming a gate oxide film on the surface of said substrate between said drain and source polycrystalline silicon regions, and drain and source diffusion regions of the second conductive type and forming a gate electrode on a top portion of the gate oxide film; forming a first insulating film on an upper surface of said nitride film and the gate electrode, and forming a window at a predetermined portion of the top portion of said source polycrystalline silicon and a storage poly contacting with the source polycrystalline silicon exposed through said window; forming a dielectric layer which becomes a dielectric substance of the stacked capacitor and a plate poly on the top portion of said storage poly; and forming a second insulating film on the top portion of said first insulating film and the plate poly and forming a window at a predetermined portion of the top portion of said drain polycrystalline silicon region, and a bit line contacting with the drain polycrystalline silicon region exposed through said window, wherein said polycrystalline silicon doped with impurities of the second conductive type and said nitride film are deposited over an entire area of the semiconductor substrate and the first and second field oxide films, said storage poly is contacted with the source polycrystalline silicon superposed on the first field oxide film, and said bit line is contacted with the drain polycrystalline silicon superposed on the second field oxide film.