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US5067105A
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System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system
Assignee: International Business Machines Corp
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Filing: 1987-11-16
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Granted: 1991-11-19
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Expires: 2007-11-16
Abstract
Abstract A system for altering physical addresses of semiconductor memory cards to locate an error-free portion to provide a contiguous range of storage which is free from errors. The system contains a memory card ID register which stores the physical addresses of memory cards in positions corresponding to logical addresses. The system evaluates the results of routine tests of memory and rearranges the physical addresses stored in the memory card ID register to provide an error-free portion at the desired logical address range. A separate memory configuration register stores a value representing the size of the memory cards. The value stored in the memory configuration register selects a subset of the logical memory address bits to obtain a logical card address. The logical card address selects a position in the memory card ID register to obtain the physical address of the memory card.
Inventors
- 👤 John M. Borkenhagen
- 👤 Quentin G. Schmierer
- 👤 Charles P. Geer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/765; G06; G06F; G06F11/00; G06F11/006
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
143 words
A method for automatically configuring the translation of a logical memory address to a physical memory address in a computer system, comprising the steps of: a. testing cards containing memory to identify those cards providing error free operation; b. storing the physical addresses of the cards so tested and providing error free operation in a card identification register at locations corresponding to a logical address range; c. reading identification data on said memory cards to determine the number of storage addresses on each card; d. translating a first portion of the logical memory address to a logical card address based on the identification data; e. accessing said register with said logical card address to obtain therefrom a physical card address; and f. combining said physical card address with a second portion of said logical memory address to obtain therefrom a physical memory address.
Claim 2
Independent Claim
143 words
A method for automatically configuring the translation of a logical memory address to a physical memory address in a computer system, comprising the steps of: a. testing cards containing memory to identify those cards providing error free operation; b. storing the physical addresses of the cards so tested and providing error free operation in a card identification register at locations corresponding to a logical address range; c. reading identification data on said memory cards to determine the number of storage addresses on each card; d. translating a first portion of the logical memory address to a logical card address based on the identification data; e. accessing said register with said logical card address to obtain therefrom a physical card address; and f. combining said physical card address with a second portion of said logical memory address to obtain therefrom a physical memory address.
Claim 3
Dependent Claim
22 words
A method according to claim 1 wherein the step of accessing said card identification register is done with the logical card address.
Claim 4
Dependent Claim
19 words
The method of claim 2 performed in real time for each memory access with only two levels of logic.
Claim 5
Independent Claim
167 words
An apparatus for automatically configuring a logical memory address to physical memory address translator in a computer system having a plurality of memory cards, wherein each of said plurality of memory cards contains identification data specifying the number of storage addresses thereon, and wherein said system has means for testing, each card to identify those cards providing error free operation, said apparatus comprising: a. memory configuration means for storing the value representing the number of storage addresses on each memory card; b. first logic means coupled to said memory configuration means for modifying a portion of said logical memory address to provide a logical card address; c. card identification means, responsive to the results of said test to identify those cards providing, error free operation, for storing the physical address of a logical card; and d. second logic means, operating in real time for each memory access and in response to said card identification means for translating said modified logical card address to a physical card address.
Claim 6
Independent Claim
167 words
An apparatus for automatically configuring a logical memory address to physical memory address translator in a computer system having a plurality of memory cards, wherein each of said plurality of memory cards contains identification data specifying the number of storage addresses thereon, and wherein said system has means for testing, each card to identify those cards providing error free operation, said apparatus comprising: a. memory configuration means for storing the value representing the number of storage addresses on each memory card; b. first logic means coupled to said memory configuration means for modifying a portion of said logical memory address to provide a logical card address; c. card identification means, responsive to the results of said test to identify those cards providing, error free operation, for storing the physical address of a logical card; and d. second logic means, operating in real time for each memory access and in response to said card identification means for translating said modified logical card address to a physical card address.
Claim 7
Dependent Claim
103 words
The apparatus automatically configuring a logical memory address to physical memory address translator of claim 4, wherein said card identification means comprises a card identification register, said register comprising a plurality of positions, each position corresponding to the logical address of a memory card and storing the physical address of that memory card; and wherein said second logic means comprises a single level of selector logic, said selector logic selecting one of the plurality of positions in said card identification register corresponding to the logical card address received from the first logic means, and providing the physical card address stored in said position.
Claim 8
Dependent Claim
50 words
The apparatus for automatically configuring a logical memory address to physical memory address translator of claim 5, wherein said first logic means comprises a single level of selector logic, said selector logic selecting a subset of address bits contained in said logical memory address to provide said logical card address.
Claim 9
Dependent Claim
50 words
The apparatus for automatically configuring a logical memory address to physical memory address translator of claim 4, wherein said first logic means comprises a single level of selector logic, said selector logic selecting a subset of address bits contained in said logical memory address to provide said logical card address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-18 | 1995-05-20 | 1995-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-18 | 1999-05-20 | 1999-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-18 | 2003-05-20 | 2003-11-19 | $7700.00 | Window Closed / Lapsed |