US5066614A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a leadframe having conductive elements preformed with solder bumps
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-09-28
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Granted: 1991-11-19
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Expires: 2010-09-28
Abstract
Abstract Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at least one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.
Inventors
- 👤 Thomas J. Dunaway
- 👤 Richard K. Spielberger
- 👤 Lori A. Dicks
- 👤 Jerald M. Loy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:56
CPC Classifications
B; B23; B23K; B23K35/00; B23K35/22; B23K35/24; B23K35/26; B23K35/268; H; H10; H10W; H10W72/00; H10W72/20
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
76 words
A method of manufacturing a bond-when-ready bumped leadframe comprising the steps of: a) providing a leadframe comprising at least one of power, ground, and signal conductive elements; and b) preforming solder bumps onto the conductive elements to provide means for selectively bonding the conductive elements to bonding locations of an electronic device, the solder bumps being preformed with a composition for maintaining a single solid phase over the temperature range of 0° C. to 150° C.
Claim 2
Independent Claim
76 words
A method of manufacturing a bond-when-ready bumped leadframe comprising the steps of: a) providing a leadframe comprising at least one of power, ground, and signal conductive elements; and b) preforming solder bumps onto the conductive elements to provide means for selectively bonding the conductive elements to bonding locations of an electronic device, the solder bumps being preformed with a composition for maintaining a single solid phase over the temperature range of 0° C. to 150° C.
Claim 3
Dependent Claim
36 words
The method of claim 1 wherein the solder bumps are preformed with a composition comprising: a) about 0.5% to about 2% by weight of tin; and b) about 98% to about 99.5% by weight of lead.
Claim 4
Independent Claim
82 words
A method of manufacturing a bond-when-ready bumped leadframe comprising the steps of: a) providing a leadframe comprising at least one of power, ground, and signal conductive elements; and b) preforming solder bumps onto the conductive elements to provide means for selectively bonding the conductive elements to bonding locations of an electronic device, the solder bumps being preformed with a composition comprising: i) about 0.5% to about 2% by weight of tin; and ii) about 98% to about 99.5% by weight of lead.
Claim 5
Independent Claim
82 words
A method of manufacturing a bond-when-ready bumped leadframe comprising the steps of: a) providing a leadframe comprising at least one of power, ground, and signal conductive elements; and b) preforming solder bumps onto the conductive elements to provide means for selectively bonding the conductive elements to bonding locations of an electronic device, the solder bumps being preformed with a composition comprising: i) about 0.5% to about 2% by weight of tin; and ii) about 98% to about 99.5% by weight of lead.
Claim 6
Independent Claim
125 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bump means comprising solder bumps positioned between corresponding leadframe conductive elements and bonding locations of the semiconductor chip, the solder bumps having a composition for maintaining a single solid phase over a temperature range of 0° C. to 150° C; and d) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 7
Independent Claim
125 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bump means comprising solder bumps positioned between corresponding leadframe conductive elements and bonding locations of the semiconductor chip, the solder bumps having a composition for maintaining a single solid phase over a temperature range of 0° C. to 150° C; and d) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 8
Independent Claim
130 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bump means comprising solder bumps positioned between corresponding leadframe conductive elements and bonding locations of the semiconductor chip, the solder bumps having a composition comprising: i) about 0.5% to about 2% by weight of tin; and ii) about 98% to about 99.5% by weight of lead. d) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 9
Independent Claim
130 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bump means comprising solder bumps positioned between corresponding leadframe conductive elements and bonding locations of the semiconductor chip, the solder bumps having a composition comprising: i) about 0.5% to about 2% by weight of tin; and ii) about 98% to about 99.5% by weight of lead. d) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 10
Independent Claim
134 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bumps preformed to the leadframe conductive elements, the solder bumps having a composition for maintaining a single solid state phase over the temperature range of 0° C. to 150° C. d) aligning the solder bumps preformed on the leadframe conductive elements with corresponding bonding locations on the semiconductor chip; and e) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 11
Independent Claim
134 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bumps preformed to the leadframe conductive elements, the solder bumps having a composition for maintaining a single solid state phase over the temperature range of 0° C. to 150° C. d) aligning the solder bumps preformed on the leadframe conductive elements with corresponding bonding locations on the semiconductor chip; and e) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 12
Independent Claim
139 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bumps preformed to the leadframe conductive elements, the solder bumps having a composition comprising: i) about 0.5% to about 2% by weight of tin; and ii) about 98% to about 99.5% by weight of lead. d) aligning the solder bumps preformed on the leadframe conductive elements with corresponding bonding locations on the semiconductor chip; and e) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 13
Independent Claim
139 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bumps preformed to the leadframe conductive elements, the solder bumps having a composition comprising: i) about 0.5% to about 2% by weight of tin; and ii) about 98% to about 99.5% by weight of lead. d) aligning the solder bumps preformed on the leadframe conductive elements with corresponding bonding locations on the semiconductor chip; and e) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 14
Independent Claim
132 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bumps preformed to the semiconductor chip bonding locations, the solder bumps having a composition for maintaining a single solid phase over the temperature range of 0° C. to 150° C.; d) aligning the solder bumps preformed on the semiconductor chip bonding pads with corresponding leadframe conductive elements; and e) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 15
Independent Claim
132 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bumps preformed to the semiconductor chip bonding locations, the solder bumps having a composition for maintaining a single solid phase over the temperature range of 0° C. to 150° C.; d) aligning the solder bumps preformed on the semiconductor chip bonding pads with corresponding leadframe conductive elements; and e) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 16
Independent Claim
138 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bumps preformed to the semiconductor chip bonding locations, the solder bumps having a composition comprising: i) about 0.5% to about 2% by weight of tin; and ii) about 98% to about 99.5% by weight of lead. d) aligning the solder bumps preformed on the semiconductor chip bonding pads with corresponding leadframe conductive elements; and e) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
Claim 17
Independent Claim
138 words
A method of manufacturing a low-cost high-strength leadframe and semiconductor chip assembly, comprising: a) providing a semiconductor chip comprising bonding locations for input and output of signals to and from the chip; b) providing leadframe means comprising at least one of power, ground, and signal conductive elements for transmitting input and output signals to the bonding locations on the semiconductor chip; c) providing solder bumps preformed to the semiconductor chip bonding locations, the solder bumps having a composition comprising: i) about 0.5% to about 2% by weight of tin; and ii) about 98% to about 99.5% by weight of lead. d) aligning the solder bumps preformed on the semiconductor chip bonding pads with corresponding leadframe conductive elements; and e) reflowing the solder bumps to join the corresponding leadframe conductive elements with the bonding locations on the semiconductor chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-18 | 1995-05-20 | 1995-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-18 | 1999-05-20 | 1999-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-18 | 2003-05-20 | 2003-11-19 | $7700.00 | Window Closed / Lapsed |