US5065218A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Locos type field isolating film and semiconductor memory device formed therewith
Assignee: Mitsubishi Electric Corp
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Filing: 1989-06-23
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Granted: 1991-11-12
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Expires: 2009-06-23
Abstract
Abstract A LOCOS isolation film is formed on a major surface of a semiconductor substrate. Thereafter, a new surface of the semiconductor substrate is exposed by wet etching. A resist pattern is formed on the exposed new surface. A part of the LOCOS isolation film is removed using this resist pattern, to expose the surface of the semiconductor substrate. This unsymmetrical LOCOS isolation film increases the effective area of the surface of the semiconductor substrate and preserves predetermined dielectric resistance.
Inventors
- 👤 Ichiro Arimoto
- 👤 Masami Yamamoto
- 👤 Tomoharu Mametani
- 👤 Ritsuko Tsutsumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:51
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
388 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a major surface, a plurality of word lines extending in parallel on the major surface of said semiconductor surface, a plurality of bit lines extending in a direction perpendicularly intersecting with said word liens on the major surface of said semiconductor substrate, memory cells formed in the vicinity of intersections of said word lines and said bit lines, said semiconductor substrate having recessed surface regions formed between adjacent said memory cells, a first configuration of insulating film for isolation provided in only a center portion of a first group of said recessed surface regions of said semiconductor substrate so that a portion of recessed surface on two sides of said first configuration of insulating film is exposed in said first group of recessed surface regions, a second configuration of insulating film for isolation provided in only a portion of each of a second group of said recessed surface regions of said semiconductor substrate so that a portion of recessed surface on one side of said second configuration of insulating film is exposed in said second group of recessed surface regions; each of said memory cells comprising a transfer gate transistor comprising a gate electrode formed on the major surface of said semiconductor substrate through an insulating film and a pair of impurity regions formed in said semiconductor substrate in a positional relation selfaligned with said gate electrode, and a charge storage element comprising an insulating film formed on said semiconductor substrate and an electrode layer formed on the surface of said insulating film; the transfer gate transistors and the charge storage elements in said memory cells being alternately arranged through said second configuration of insulating film for isolation in a direction in which said word lines extend, charge storage elements extending into said recessed surface regions of said second group to contact to said second configuration of insulating film for isolation, charge storage elements in adjacent memory cells being arranged through said first configuration of insulating film for isolation in a direction in which said bit lines extend, charge storage elements on two sides of each of said recessed surface regions of said first group extending into said recessed surface regions of said semiconductor substrate to contact said first configuration of insulating film for isolation.
Claim 2
Dependent Claim
388 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a major surface, a plurality of word lines extending in parallel on the major surface of said semiconductor surface, a plurality of bit lines extending in a direction perpendicularly intersecting with said word liens on the major surface of said semiconductor substrate, memory cells formed in the vicinity of intersections of said word lines and said bit lines, said semiconductor substrate having recessed surface regions formed between adjacent said memory cells, a first configuration of insulating film for isolation provided in only a center portion of a first group of said recessed surface regions of said semiconductor substrate so that a portion of recessed surface on two sides of said first configuration of insulating film is exposed in said first group of recessed surface regions, a second configuration of insulating film for isolation provided in only a portion of each of a second group of said recessed surface regions of said semiconductor substrate so that a portion of recessed surface on one side of said second configuration of insulating film is exposed in said second group of recessed surface regions; each of said memory cells comprising a transfer gate transistor comprising a gate electrode formed on the major surface of said semiconductor substrate through an insulating film and a pair of impurity regions formed in said semiconductor substrate in a positional relation selfaligned with said gate electrode, and a charge storage element comprising an insulating film formed on said semiconductor substrate and an electrode layer formed on the surface of said insulating film; the transfer gate transistors and the charge storage elements in said memory cells being alternately arranged through said second configuration of insulating film for isolation in a direction in which said word lines extend, charge storage elements extending into said recessed surface regions of said second group to contact to said second configuration of insulating film for isolation, charge storage elements in adjacent memory cells being arranged through said first configuration of insulating film for isolation in a direction in which said bit lines extend, charge storage elements on two sides of each of said recessed surface regions of said first group extending into said recessed surface regions of said semiconductor substrate to contact said first configuration of insulating film for isolation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-11 | 1995-05-13 | 1995-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-11 | 1999-05-13 | 1999-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-11 | 2003-05-13 | 2003-11-12 | $7700.00 | Window Closed / Lapsed |