Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
206 words
A data processing device allowing a direct memory-access operation to be performed between a read/write memory and an I/O interface, said data processing device comprising: interrupt detecting means for detecting an interrupt signal and for generating a vector corresponding to the detected interrupt signal; control signal generating means for generating, in response to said vector, a control signal indicating whether said interrupt signal is a normal interrupt signal or a direct memory-access interrupt signal; logical operation processing means, having a ROM storing micro-code instructions for executing a normal operation, a normal interrupt operation, and a direct memory-access operation, for sequentially reading out the micro-code instructions in order to control the execution of the normal operation and the normal interrupt operation, and for sequentially reading out the micro-code instructions in order to control the execution of the direct memory access operation when a control signal is generated by said control signal generating means in accordance with the interrupt signal requesting the direct memory access operation; and parameter memory means for, upon the execution of said direct memory-access operation, storing parameters for use by said logical operation processing means, for reading said parameters responsive to said vector, and for supplying said parameters to said logical operation processing means.
Claim 2
Dependent Claim
206 words
A data processing device allowing a direct memory-access operation to be performed between a read/write memory and an I/O interface, said data processing device comprising: interrupt detecting means for detecting an interrupt signal and for generating a vector corresponding to the detected interrupt signal; control signal generating means for generating, in response to said vector, a control signal indicating whether said interrupt signal is a normal interrupt signal or a direct memory-access interrupt signal; logical operation processing means, having a ROM storing micro-code instructions for executing a normal operation, a normal interrupt operation, and a direct memory-access operation, for sequentially reading out the micro-code instructions in order to control the execution of the normal operation and the normal interrupt operation, and for sequentially reading out the micro-code instructions in order to control the execution of the direct memory access operation when a control signal is generated by said control signal generating means in accordance with the interrupt signal requesting the direct memory access operation; and parameter memory means for, upon the execution of said direct memory-access operation, storing parameters for use by said logical operation processing means, for reading said parameters responsive to said vector, and for supplying said parameters to said logical operation processing means.
Claim 3
Dependent Claim
54 words
A data processing device according to claim 1, wherein said control signal generating means includes a register for storing data indicating whether said interrupt signal is a normal interrupt or an interrupt for requesting the direct memory-access operation, and data select means for selecting the data of said register in response to said vector.
Claim 4
Dependent Claim
45 words
The data processing device according to claim 1, wherein said parameter memory means stores a command, a data transfer source address, a data transfer destination address, and a data transfer number, used when said direct memory-access operation is executed by said logical operation processing means.
Claim 5
Dependent Claim
40 words
The data processing device according to claim 3, wherein said data transfer source address, said data transfer destination address, and said data transfer number stored in said parameter memory means are updated under control of said logical operation processing means.
Claim 6
Dependent Claim
17 words
The data processing device according to claim 1, wherein said parameter memory means includes a read/write memory.