Memory access control system

Claim 2

A memory access control system including an integral assembly of a central processing unit and a direct memory access controller, said integral assembly generating commands and request signals, said system comprising: a main memory; an I/O device; bus means interconnecting said memory and said I/O device to each other, to said central processing unit, and to said direct memory access controller; means for generating a logic signal representing the logic status of a predetermined bit position in a said generated command; a bus controller for generating a control signal in response to said logic signal and to a request signal from said integral assembly a bus switch connected to said bus means and responsive to said control signal, said bus switch controlling said bus means to place said memory and said I/O device under the control of said integral assembly when said bus controller receives a logic signal representative of one logic status of said predetermined bit position and to perform a cycle steal memory access between said memory and said I/O device when said bus controller receives a logic signal representative of another logic status of said predetermined bit position.

Claim 3

A memory access control system comprising: an integral assembly of a central processing unit and a direct memory access controller, said integral assembly generating commands and requests; a main memory; an I/O device; bus means interconnecting said memory and said I/O device to each other, to said central processing unit, and to said direct memory access controller; means for generating a first logic signal representing the logic status of a predetermined bit position in a said generated command; means for generating program status words; means for generating a second logic signal in response to the contents of a said program status word; logic gate circuit means for generating specific signals in response to said first and second logic signals; a bus controller for generating a bus switch control signal in response to both said specific signal and a request signal from said integral assembly; and a bus switch responsive to said control signal, said bus switch controlling said bus to place said memory and said I/O device under the control of said integral assembly when said bus controller receives a particular one of said special signals from said logic gate circuit in response to a predetermined relationship between the contents of said program status word and one logic status of said predetermined bit position and to perform a cycle steal memory access between said memory and said I/O device when said bus controller receives a second particular one of sid special signals from said logic gate circuit in response to a predetermined relationship between the contents of said program status word and another logic status of said predetermined bit position.

Claim 4

A memory access control system comprising: an integral assembly of a central processing unit and a direct memory access controller, said integral assembly generating commands and requests; a main memory; an I/O device; bus means interconnecting said memory and said I/O device to each other, to said central processing unit, and to said direct memory access controller; means for generating a first logic signal representing the logic status of a predetermined bit position in a said generated command; means for generating program status words; means for generating a second logic signal in response to the contents of a said program status word; logic gate circuit means for generating specific signals in response to said first and second logic signals; a bus controller for generating a bus switch control signal in response to both said specific signal and a request signal from said integral assembly; and a bus switch responsive to said control signal, said bus switch controlling said bus to place said memory and said I/O device under the control of said integral assembly when said bus controller receives a particular one of said special signals from said logic gate circuit in response to a predetermined relationship between the contents of said program status word and one logic status of said predetermined bit position and to perform a cycle steal memory access between said memory and said I/O device when said bus controller receives a second particular one of sid special signals from said logic gate circuit in response to a predetermined relationship between the contents of said program status word and another logic status of said predetermined bit position.