High density input/output cell arrangement for integrated circuits

Abstract

Abstract A high density arrangement of input/output pad cells for general application, but especially useful in non-pad limited design because it conserves substrate area that is not needed for pad cells. The pad cells have their transistors, protection diodes and integrated pull up resistors located in a linear array between the physical pads where the electrical leads make contact. Each pad cell has a bank of N-FETs on one of its lateral sides and a bank of P-FETs on its opposite lateral side. By interchanging the location of the banks of N-FETs and P-FETs of adjacent pad cells relative to the physical pad, a high density arrangement is achieved that is not prone to forming parasitic thyristors or the latch-up problem associated with such parasitic thyristors. The pad cells are shielded from noise pulses and surges on their outer perimeter by a two level power bus, and on their inner perimeter by a similar two level power bus. Connections to and from the pad cells are made by polysilicon conductors located beneath the inner two level power bus. This high density arrangement not only conserves silicon area, but also virtually eliminates latch-up causing noise from passing through the input/output pad cell region.

Inventors

• 👤 Harold S. Crafts

Bibliographic Details