US5063307A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Insulated gate transistor devices with temperature and current sensor
Assignee: IXYS LLC
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Filing: 1990-09-20
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Granted: 1991-11-05
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Expires: 2010-09-20
Abstract
Abstract A technique for sensing the temperature of power MOS devices contemplates a main transistor and monolithically formed sense transistor. A resistor, which may integrated into the device or may be off chip, is connected between the respective source nodes of the main transistor and the sense transistor (as in a normal current mirror). However, the respective gate nodes of the main transistor and the sense transistor are not directly connected to each other (in contrast to the normal current mirror configuration where the respective gate nodes of the main transistor and the sense transistor are directly connected). Rather, the sense transistor gate node is coupled to the output terminal of an operational amplifier. The amplifier, has a first input terminal coupled to a reference voltage and a second, complementary, input terminal coupled to the sense transistor source node.
Inventors
- 👤 Nathan Zommer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/669; H03; H03K; H03K17/00; H03K17/08; H03K17/082; H03K17/0822; H03K17/51; H03K17/56; H03K17/567; H10D89/00; H10D89/60; H03K2017/0806
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
162 words
A semiconductor device in combination with temperature sensing circuitry comprising: a first insulated gate transistor having a first drain node, a first gate node, and a first source node; a second insulated gate transistor, monolithic with and much smaller than said first transistor, having a second drain node, a second gate node, and a second source node; said first and second drain nodes having a common connection; a resistor coupled between said first and second source nodes; means defining a reference voltage; and an operational amplifier having a first input terminal coupled to said reference voltage, a second complementary input terminal coupled to said second source node, and an output terminal coupled to said second gate node; whereupon when current flows from said second drain node, through said second gate insulated transistor, through said resistor, and to said second source node, the voltage appearing at said second gate terminal provides a direct measure of the temperature of said second insulated gate transistor.
Claim 2
Dependent Claim
162 words
A semiconductor device in combination with temperature sensing circuitry comprising: a first insulated gate transistor having a first drain node, a first gate node, and a first source node; a second insulated gate transistor, monolithic with and much smaller than said first transistor, having a second drain node, a second gate node, and a second source node; said first and second drain nodes having a common connection; a resistor coupled between said first and second source nodes; means defining a reference voltage; and an operational amplifier having a first input terminal coupled to said reference voltage, a second complementary input terminal coupled to said second source node, and an output terminal coupled to said second gate node; whereupon when current flows from said second drain node, through said second gate insulated transistor, through said resistor, and to said second source node, the voltage appearing at said second gate terminal provides a direct measure of the temperature of said second insulated gate transistor.
Claim 3
Dependent Claim
16 words
The combination device of claim 1 wherein said first and second insulated gate transistors are MOSFETs.
Claim 4
Dependent Claim
16 words
The combination device of claim 1 wherein said first and second insulated gate transistors are IGBTs.
Claim 5
Dependent Claim
49 words
The combination of claim 1, and further comprising switching means for disconnecting said operational amplifier's output terminal from said second gate node and for connecting said second to said first gate node, whereby the voltage appearing across said resistor provides a representation of the current flowing through the device.
Claim 6
Dependent Claim
18 words
The combination of claim 1 wherein said first and second insulated gate transistors are n-channel enhancement mode devices.
Claim 7
Dependent Claim
19 words
The combination of claim 1 wherein said resistor is formed monolithically with said first and second insulated gate transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-11-04 | 1995-05-06 | 1995-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-04 | 1999-05-06 | 1999-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-04 | 2003-05-06 | 2003-11-05 | $7700.00 | Window Closed / Lapsed |