← Back to Patent Explorer
US4785207A Expired / Lapsed US ⏱️ 0.0 years remaining

Leakage regulator circuit for a field effect transistor

Assignee: Huges Aircraft Company A Corp Of De
•
Filing: 1987-01-21
•
Granted: 1988-11-15
•
Expires: 2007-01-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A leakage regulator for use with switching power supplies which include a field effect transistor (FET) is disclosed. The leakage regulator comprises a bias circuit coupled in a feedback arrangement with the FET to provide a self-generated bias voltage. The bias circuit includes a current transformer coupled to receive a drain-source leakage current. A bias voltage is generated from the transformed leakage current and this bias voltage is applied to the FET gate to help decrease the leakage current.

Inventors

  • 👤 John E. Eng

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 22:01
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/165; H03K19/00; H03K19/003; H03K19/0033; H03K19/00338; H03K19/00346; H03K19/00361

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 66 words
An FET bias circuit for providing a bias voltage to an FET having a gate, a source and a drain to reduce drain-source leakage current in said FET, said circuit comprising: a current transformer, coupled in series with said FET, for generating said bias voltage in response to the leakage current; and means for coupling said bias voltage from said generating means to said FET gate.
Claim 2
Dependent Claim 66 words
An FET bias circuit for providing a bias voltage to an FET having a gate, a source and a drain to reduce drain-source leakage current in said FET, said circuit comprising: a current transformer, coupled in series with said FET, for generating said bias voltage in response to the leakage current; and means for coupling said bias voltage from said generating means to said FET gate.
Claim 3
Dependent Claim 26 words
The bias circuit of claim 1, wherein said FET is an n-channel MOSFET and said current transformer is coupled between said source and a ground terminal.
Claim 4
Dependent Claim 26 words
The bias circuit of claim 1, wherein said FET is an n-channel MOSFET and said current transformer is coupled between said drain and a voltage supply.
Claim 5
Dependent Claim 47 words
The bias circuit of claim 1, and further comprisinq a capacitor coupled in parallel with the secondary side of said current transformer for storing a charge from said transformer to provide said bias voltage, and wherein one side of said capacitor is coupled to said FET gate.
Claim 6
Dependent Claim 27 words
The bias circuit of claim 4, and further including means coupled in parallel with said transformer secondary for shorting-out said transformer when said FET is turned on.
Claim 7
Independent Claim 59 words
A method for reducing drain-source leakage current in an FET having a gate, a source and a drain, comprising the steps of: generating a bias voltage in response to the leakage current using a current transformer coupled in series with said FET to receive the drain-source leakage current; and applying said bias voltage to said gate of said FET.
Claim 8
Independent Claim 59 words
A method for reducing drain-source leakage current in an FET having a gate, a source and a drain, comprising the steps of: generating a bias voltage in response to the leakage current using a current transformer coupled in series with said FET to receive the drain-source leakage current; and applying said bias voltage to said gate of said FET.
Claim 9
Dependent Claim 22 words
The method of claim 6 and further including the step of shorting out said current transformer when said FET is turned on.
Claim 10
Dependent Claim 12 words
The method of claim 6, wherein said FET is an N-channel MOSFET.

References Cited (Backward Citations)

US3521141A Cited
US4074344A Cited
US4360744A Cited
US4430608A Cited
US4446390A Cited
US4590456A Cited
US4617481A Cited
US4544854A Cited
US4642485A Cited
US4691129A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-11-15 1992-05-16 1992-11-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-11-15 1996-05-16 1996-11-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-11-15 2000-05-16 2000-11-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag