US4590456A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low leakage CMOS D/A converter
Assignee: Analog Devices Inc
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Filing: 1985-08-06
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Granted: 1986-05-20
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Expires: 2005-08-06
Abstract
Abstract A CMOS DAC with means to avoid leakage current. In one embodiment, the back gates of the CMOS switches are held at -200 mV with respect to the output lines, and the logic low level to the off switch also is set at -200 mV relative to the output lines. In another embodiment, the CMOS switches are ion-implanted. In a still further embodiment, the output lines are held at a potential 200 mV more positive than the P- well of the CMOS switches.
Inventors
- 👤 David P. Burton
- 👤 Peter Real
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:18
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74; H03M1/78; H03M1/785
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
108 words
In a CMOS digital-to-analog converter comprising at least one switch-pair in a common well, the individual switches of such pair being complementarily driven to "on" and "off" condition respectively to switch a corresponding resistance network terminal to one or the other of a pair of output lines in accordance with the state of an input bit, each switch having a driving gate and a back gate; that improvement in such a converter for reducing leakage current comprising: bias means to develop a predetermined potential difference between said output lines and said well with said well being more negative than said output lines, thereby to avoid bipolar leakage current.
Claim 2
Dependent Claim
108 words
In a CMOS digital-to-analog converter comprising at least one switch-pair in a common well, the individual switches of such pair being complementarily driven to "on" and "off" condition respectively to switch a corresponding resistance network terminal to one or the other of a pair of output lines in accordance with the state of an input bit, each switch having a driving gate and a back gate; that improvement in such a converter for reducing leakage current comprising: bias means to develop a predetermined potential difference between said output lines and said well with said well being more negative than said output lines, thereby to avoid bipolar leakage current.
Claim 3
Dependent Claim
30 words
A converter as claimed in claim 1, wherein said bias means is operable to bias said well negative with respect to ground, thereby to bias the switch back gates correspondingly.
Claim 4
Dependent Claim
22 words
A converter as claimed in claim 2, including means to drive the off gate voltage negative with respect to said output lines.
Claim 5
Dependent Claim
30 words
A converter as claimed in claim 3, where the off gate voltage is in the range of about 150 mV to 500 mV negative with respect to said output lines.
Claim 6
Dependent Claim
23 words
A converter as claimed in claim 4, where said off gate voltage is about 200 mV negative with respect to said output lines.
Claim 7
Dependent Claim
18 words
A converter as claimed in claim 2, wherein said negatively-biased well includes the switch drivers for said switches.
Claim 8
Dependent Claim
19 words
A converter as cliamed in claim 6, including a second well forming a diode for developing the bias voltage.
Claim 9
Dependent Claim
28 words
A converter as claimed in claim 7, including either diffused resistors on said second well or thin-film resistors for scaling down the diode voltage to the proper level.
Claim 10
Dependent Claim
17 words
A converter as claimed in claim 2, wherein said switches are ion-implanted to avoid subthreshold leakage current.
Claim 11
Dependent Claim
34 words
A converter as claimed in claim 1, including output op amp means connected to said output lines respectively; and a positive bias voltage source connected to said op-amp means to produce said potential difference.
Claim 12
Dependent Claim
54 words
A converter as claimed in claim 10, wherein said op-amp means comprises an op amp with its input terminals connected to said output lines respectively; a negative feedback resistor connected between the op-amp output and its negative input terminal; said positive bias voltage source being connected to the positive input of said op amp.
Claim 13
Dependent Claim
22 words
A converter as claimed in claim 11, wherein the bias voltage is in the range of about 150 mV to 500 mV.
Claim 14
Dependent Claim
22 words
A converter as claimed in claim 1, wherein said potential difference is in the range of about 150 mV to 500 mV.
Claim 15
Dependent Claim
15 words
A converter as claimed in claim 13, wherein said potential difference is about 200 mV.
Claim 16
Dependent Claim
30 words
A converter as claimed in claim 1, wherein said common well is P-type in an N-type substrate; said output lines being connected to an N-type region within said common well.
References Cited (Backward Citations)
US3984830A
Cited
US4446390A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-19 | 1989-11-18 | 1990-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-19 | 1993-11-18 | 1994-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-19 | 1997-11-18 | 1998-05-20 | $7700.00 | Window Closed / Lapsed |