Amplifier circuit free from leakage between input and output ports

Claim 2

A circuit comprising: an input terminal receiving an input signal; a reference potential terminal; an output terminal for receiving an output signal; an operational amplifier having an inverting input port connected to said input termihal, a non-inverting input port connected to said reference potential terminal, and an output port connected to said output terminal; a first switch connected between said inverting input port and a first connection node; a second switch connected between said first connection node and said output terminal; a third switch connected between said first connection node and said reference potential terminal; and a means for controlling said first, second, and third switches, said switch controlling means operatively closing said first and second switches simultaneously and operatively closing said third switch when said first and second switches are opened so that the potential difference between said first connection node and said inverting port is reduced when said first and second switches are open to prevent leakage current from flowing between said inverting input port and said output port of said operational amplifier.

Claim 3

A circuit as claimed in claim 1, further comprising a fourth switch having between said input terminal and a second connection node, a first capacitor inserted between said second connection node and said inverting input port of said amplifier, and a fifth switch inserted between said reference potential terminal and said second connection node, said fourth switch being controlled to be closed together with said third switch, and said fifth switch being controlled to be closed and opened together with said first and second switches.

Claim 4

A circuit as claimed in claim 2, wherein said first, second, third, fourth and fifth switches are made of field effect transistors.

Claim 5

A circuit as claimed in claim 2, further comprising a second capacitor inserted between said inverting input port and said output port of said amplifier.

Claim 6

A circuit as claimed in claim 4, wherein said first, second, third, fourth and fifth switches are made of field effect transistors.

Claim 7

A circuit comprising: an input terminal receiving an input signal; a reference potential terminal; an output terminal for receiving an output signal; a first switch connected between said input terminal and a first connection node; a second switch connected between said first connection node and said reference potential terminal; a first capacitor connected between said first connection node and a second connection node; an amplifier having an inverting input port connected to said second connection node, an non-inverting input port connected to said reference potential terminal, and an output port connected to said output terminal; a third switch connected between said second connection node and a third connection node; a fourth switch connected between said third connection node and said output port; a fifth switch connected between said third connection node and said reference potential terminal; and a means for controlling said first, second, third, fourth, and fifth switches, said switch controlling means alternately generating a first phase in which said first switch and said fifth switch are opened and said second switch, said third switch, and said fourth switch are closed, and a second phase in which said first switch and said fifth switch are closed and said second switch, said third switch, and said fourth switch are opened.

Claim 8

A circuit comprising: an input terminal receiving an input signal; a reference potential terminal; an output terminal for receiving an output signal; a first switch connected between said input terminal and a first connection node; a second switch connected between said first connection node and said reference potential terminal; a first capacitor connected between said first connection node and a second connection node; an amplifier having an inverting input port connected to said second connection node, an non-inverting input port connected to said reference potential terminal, and an output port connected to said output terminal; a third switch connected between said second connection node and a third connection node; a fourth switch connected between said third connection node and said output port; a fifth switch connected between said third connection node and said reference potential terminal; and a means for controlling said first, second, third, fourth, and fifth switches, said switch controlling means alternately generating a first phase in which said first switch and said fifth switch are opened and said second switch, said third switch, and said fourth switch are closed, and a second phase in which said first switch and said fifth switch are closed and said second switch, said third switch, and said fourth switch are opened.

Claim 9

The circuit according to claim 6, further comprising a second capacitor connected between said second connection node and said output port.

Claim 10

A coefficient multiplying circuit comprising: an input terminal receiving an input signal; a reference potential terminal; an amplifier having an inverting input port, a non-inverting input port connected to said reference potential terminal, and an output port; a first capacitor having one end connected to said inverting input port; a first means coupled between said input terminal and the other end of said capacitor for charging said first capacitor in accordance with said input signal; a second capacitor coupled between said inverting input port and said output port; first and second switches connected in series between said inverting input port and said output port; a third switch coupled between the connection node of said first and second switches and said reference potential terminal; and a second means for controlling said first and second switches simultaneously and said third switch in an opposite mode, so that the potential difference between said first connection node and said inverting input port is reduced when said first and second switches are open to prevent leakage current from flowing between said inverting input port and said output port of said operational amplifier.

Claim 11

A coefficient multiplying circuit comprising: an input terminal receiving an input signal; a reference potential terminal; an amplifier having an inverting input port, a non-inverting input port connected to said reference potential terminal, and an output port; a first capacitor having one end connected to said inverting input port; a first means coupled between said input terminal and the other end of said capacitor for charging said first capacitor in accordance with said input signal; a second capacitor coupled between said inverting input port and said output port; first and second switches connected in series between said inverting input port and said output port; a third switch coupled between the connection node of said first and second switches and said reference potential terminal; and a second means for controlling said first and second switches simultaneously and said third switch in an opposite mode, so that the potential difference between said first connection node and said inverting input port is reduced when said first and second switches are open to prevent leakage current from flowing between said inverting input port and said output port of said operational amplifier.

Claim 12

A coefficient multiplying circuit according to claim 8, wherein said first means includes a fourth switch connected between said input terminal and the other end of said first capacitor.