High power transistor with voltage, current, power, resistance, and temperature sensing capability

Claim 2

A power MOSFET comprising: a volume of semiconductor doped to a first conductivity type; first and second pluralities of MOSFET cells formed in respective first and second regions of said semiconductor volume, each MOSFET cell having a region doped to a second conductivity type opposite said first conductivity type and having a source region formed therein of said first conductivity type; and a plurality of isolation cells formed in a third region of said semiconductor volume disposed between said first and second regions, said isolation cells each having a region of said second conductivity type, but no source region.

Claim 3

A power MOSFET comprising: a volume of semiconductor doped to a first conductivity type; first and second pluralities of MOSFET cells formed in respective first and second regions of said semiconductor volume, each MOSFET cell having a region doped to a second conductivity type opposite said first conductivity type and having a source region formed therein of said first conductivity type; and a guard ring of said second conductivity type formed in a third region of said semiconductor disposed between said first and second regions.

Claim 4

A power MOSFET comprising: a volume of semiconductor doped to a first conductivity type; first and second pluralities of MOSFET cells formed in respective first and second regions of said semiconductor volume, each MOSFET cell having a region doped to a second conductivity type opposite said first conductivity type and having a source region formed therein of said first conductivity type; and a guard ring of said second conductivity type formed in a third region of said semiconductor disposed between said first and second regions.

Claim 5

A power MOSFET in combination with voltage sensing circuitry comprising: a semiconductor volume; first and second sets of MOSFET cells formed in respective first and second regions of said semiconductor volume, each cell having a source and drain between which current flow may be established, said first set of cells having a relatively large number of cells and said second set of cells having a much smaller number of cells; each set of cells having commonly connected drains and commonly connected sources, the commonly connected drains of said first and second sets of cells having a common connection, the commonly connected source of said first set and said second set of cells being electrically isolated from each other to provide separate first and second source nodes; and a resistor having a resistance substantially greater than the on-resistance of said second set of cells, coupled between said second source node and said first source node for providing a voltage level that closely approximates the voltage level at the common drain connection.

Claim 6

A power MOSFET in combination with voltage sensing circuitry comprising: a semiconductor volume; first and second sets of MOSFET cells formed in respective first and second regions of said semiconductor volume, each cell having a source and drain between which current flow may be established, said first set of cells having a relatively large number of cells and said second set of cells having a much smaller number of cells; each set of cells having commonly connected drains and commonly connected sources, the commonly connected drains of said first and second sets of cells having a common connection, the commonly connected source of said first set and said second set of cells being electrically isolated from each other to provide separate first and second source nodes; and a resistor having a resistance substantially greater than the on-resistance of said second set of cells, coupled between said second source node and said first source node for providing a voltage level that closely approximates the voltage level at the common drain connection.

Claim 7

The combination of claim 3 wherein said resistor is external to said semiconductor.

Claim 8

The combination of claim 3 wherein said resistor is formed on said semiconductor.

Claim 9

A power MOSFET in combination with current and voltage sensing circuitry comprising: a semiconductor volume; first, second and third sets of MOSFET cells formed in respective first, second and third regions of said semiconductor volume, each cell having a source and drain between which current flow may be established, said first set of cells having a relatively large number of cells and said second and third set of cells each having a much smaller number of cells; each set of cells having commonly connected drains and commonly connected sources, the commonly connected drains of said first, second and third sets of cells having a common connection, the commonly connected source of said first set, said second set, and said third set of cells being electrically isolated from each other to provide separate first, second and third source nodes; a first resistor having a resistance substantially less than the on-resistance of said second set of cells, coupled between said second source node and said first source node for providing a voltage at said second source node representative of the current flowing in said first set of cells; and a second resistor having a resistance substantially greater than the on-resistance of said third set of cells, coupled between said third source node and said first source node for providing a voltage at said third source node that closely approximates the voltage level at said common drain connection.

Claim 10

A power MOSFET in combination with current and voltage sensing circuitry comprising: a semiconductor volume; first, second and third sets of MOSFET cells formed in respective first, second and third regions of said semiconductor volume, each cell having a source and drain between which current flow may be established, said first set of cells having a relatively large number of cells and said second and third set of cells each having a much smaller number of cells; each set of cells having commonly connected drains and commonly connected sources, the commonly connected drains of said first, second and third sets of cells having a common connection, the commonly connected source of said first set, said second set, and said third set of cells being electrically isolated from each other to provide separate first, second and third source nodes; a first resistor having a resistance substantially less than the on-resistance of said second set of cells, coupled between said second source node and said first source node for providing a voltage at said second source node representative of the current flowing in said first set of cells; and a second resistor having a resistance substantially greater than the on-resistance of said third set of cells, coupled between said third source node and said first source node for providing a voltage at said third source node that closely approximates the voltage level at said common drain connection.

Claim 11

The combination of claim 6 wherein said third set of cells has fewer cells than said second set of cells.

Claim 12

The combination of claim 6 wherein at least one of said resistors is external to said semiconductor volume.

Claim 13

The combination of claim 6 wherein at least one of said resistors is formed on said semiconductor volume.

Claim 14

A power MOSFET in combination with current and voltage sensing circuitry, comprising: a semiconductor volume; first and second sets of MOSFET cells formed in respective first and second regions of said semiconductor volume, each cell having a source and drain between which current flow may be established, said first set of cells having a relatively large number of cells and said second set of cells having a much smaller number of cells; each set of cells having commonly connected drains and commonly connected sources, the commonly connected drains of said first and second sets of cells having a common connection, the commonly connected source of said first set and said second set of cells being electrically isolated from each other to provide separate first and second source nodes; and means, having at least first and second states, for establishing (a) in said first state a first resistance, substantially less than the on-resistance of said second set of cells, between said second source node and said first source node so as to provide a voltage at said second source node that is representative of the current through said second set of cells, and (b) in said second state, a second resistance, substantially greater than the on-resistance of said second set of cells, between said second source node and said first source node so as to provide a voltage at said second source node that closely approximates the voltage level at the common drain connection.

Claim 15

A power MOSFET in combination with current and voltage sensing circuitry, comprising: a semiconductor volume; first and second sets of MOSFET cells formed in respective first and second regions of said semiconductor volume, each cell having a source and drain between which current flow may be established, said first set of cells having a relatively large number of cells and said second set of cells having a much smaller number of cells; each set of cells having commonly connected drains and commonly connected sources, the commonly connected drains of said first and second sets of cells having a common connection, the commonly connected source of said first set and said second set of cells being electrically isolated from each other to provide separate first and second source nodes; and means, having at least first and second states, for establishing (a) in said first state a first resistance, substantially less than the on-resistance of said second set of cells, between said second source node and said first source node so as to provide a voltage at said second source node that is representative of the current through said second set of cells, and (b) in said second state, a second resistance, substantially greater than the on-resistance of said second set of cells, between said second source node and said first source node so as to provide a voltage at said second source node that closely approximates the voltage level at the common drain connection.

Claim 16

The combination of claim 10 wherein said means for establishing comprises: a first resistor having a resistance substantially less than the on-resistance of said second set of cells, coupled between an intermediate node and said first source node; a second resistor having a resistance substantially greater than the on-resistance of said second set of cells, coupled between said second source node and said first source node; and a switch coupled between said second source node and said intermediate node, whereupon when said switch is closed, the resistance between said second source node and said first source node approximates the resistance of said first resistor and when said switch is open, the resistance between said second source node and said first source node equals the resistance of said second resistor.