Processor/coprocessor interface apparatus including microinstruction clock synchronization

Claim 2

An information processing system including a first data processing means and a second data processing means each of which includes means for independently executing macroinstructions during one or more microinstruction cycles having a period that is a multiple of a period of a repetitive unit clock signal, each of the data processing means including means, having an input coupled to the unit clock signal and an input coupled to a request for sychronization signal generated by the other data processing means, for generating an associated microinstruction cycle clock signal having a period that is a multiple of the period of the unit clock signal, the microinstruction cycle clock signal generating means further comprising means, responsive to an assertion of the request for synchrozintation signal, for suspending the generation of the microinstruction cycle clock signal and for beginning a next microinstruction cycle clock signal, in synchronism with the other data processing means beginning a next microinstruction clock signal, upon a transition of the unit clock signal.

Claim 3

An information processing system as set forth in claim 1 wherein both the first data processing means and the second data processing means each comprise means for generating at least one output signal for indicating that the associated data processing means is executing a final microinstruction of a macroinstruction, the output signal of each of the data processing means being coupled to an input of the generating means of the other data processing means.

Claim 4

An information processing system as set forth in claim 1 and further comprising memory means addressed by the first data processing means, the memory means having a bidirectional data bus coupled at least to the second data processing means.

Claim 5

An information processing system as set forth in claim 1 and further comprising a memory means addressed by the first data processing means, the memory means having a bidirectional data bus coupled at least to both the first and second processing means, the first data processing means further comprising an instruction register means for storing a macroinstruction read from the memory means, the instruction register means having an output coupled to the second data processing means.

Claim 6

An information processing system as set forth in claim 4 wherein the first data processing means comprises instruction decoding means coupled to the output of the instruction register means for detecting macroinstructions which are executed by the second data processing means.

Claim 7

An information processing system as set forth in claim 5 wherein the detected macroinstructions include macroinstructions which operate on operands stored at address locations within the memory means, and wherein the first data processing means further includes at least one address output signal which is coupled to and received by the second data processing means, the at least one address output signal indicating a portion of the address location within the memory means of an operand associated with one of the detected macroinstructions.

Claim 8

An information processing system as set forth in claim 6 wherein the at least one address output signal further indicates a location, relative to an address, of the operand within the memory means.

Claim 9

An information processing system as set forth in claim 7 wherein, for a first type of macroinstruction, the instruction register means output includes a first plurality of signals for indicating, in conjunction with the at least one address output signal, a number of memory means storage locations occupied by an operand that is referenced by the first type of macroinstruction.

Claim 10

An information processing system as set forth in claim 8 wherein the second data processing means further comprises determining means responsive to the at least one address output signal, and also to the first plurality of instruction register means output signals, for determining a number of memory means access cycles required to completely read the operand from the memory means.

Claim 11

An information processing system as set forth in claim 9 wherein the second data processing means further comprises a plurality of output signals which are driven by the determining means and which are coupled to the first data processing means for indicating to the first data processing means the determined number of memory means access cycles.

Claim 12

An information processing system as set forth in claim 7 wherein the second data processing means further comprises means, having an input coupled coupled to the at least one address signal, for asserting a plurality of memory means write enable output signals which are coupled to the memory means for enabling only those locations within the memory means which are occupied by the operand, predetermined ones of the plurality of memory means write enable signals being asserted by the second data processing means to store a result of a macroinstruction which operates on the operand, the result being stored within the memory means at the storage locations occupied by the operand.

Claim 13

An information processing system as set forth in claim 11 wherein the second data processing means further includes means, responsive to the operation of the asserting means, for providing an output signal which is coupled to the first data processing means for informing the first data processing means of an exception condition, including a condition wherein a result of the execution of a macroinstruction requires more memory means storage locations than are occupied by the first operand.

Claim 14

An information processing system as set forth in claim 5 wherein the second data processing means includes a plurality of floating point register means and wherein the instruction register means output includes a first plurality of signals for identifying one of the floating point register means to be loaded with a first operand associated with a detected macroinstruction, and wherein the instruction register output further includes a second plurality of signals for identifying another one of the floating point register means associated with a second operand.

Claim 15

An information processing system as set forth in claim 5 wherein the instruction decoding means further detects other macroinstructions which are executed by the first data processing means and which require, before execution, the termination of execution of a macroinstruction by the second data processing means.

Claim 16

An information processing system as set forth in claim 14 wherein the second data processing means further includes means for indicating the termination of execution of a macroinstruction and wherein the generating means further comprises means, coupled to and responsive to the operation of the instruction termination indicating means, for enabling the execution of one of the other macroinstructions after the second data processing means terminates execution of a macroinstruction.

Claim 17

An information processing system as set forth in claim 15 wherein the other macroinstructions include conditional branch instructions, and wherein the second data processing means further includes a plurality of condition code output signals which are coupled to the first data processing means for informing the first data processing means of condition generated by the execution of a macroinstruction.

Claim 18

An information processing system comprising: memory means; first data processing means comprising means for addressing the memory means wherein instructions and operands related to instructions are stored; second data processing means comprising means for executing a first plurality of the instructions, the second data processing means being coupled to the memory means for reading therefrom operands associated with certain ones of the first plurality of instructions and for storing within the memory means a result of the certain instructions which operate on the operands; the system further comprising an interface means coupled between the first and the second data processing means, the interface means including a plurality of signals coupled to both the first and the second data processing means, the plurality of signals comprising: a repetitive unit clock signal having a substantially constant period associated therewith, the unit clock signal being received by both the first and the second data processing means; an instruction signal generated by the first data processing means and received by the second data processing means, the instruction signal being expressive of at least which one of the predetermined instructions is to be executed by the second data processing means; a first end of cycle signal asserted by the first data processing means and received by the second data processing means, the first end of cycle signal indicating, when asserted, that the first data processing means can be synchronized with the second data processing means; a second end of cycle signal asserted by the second data processing means and received by the first data processing means, the second end of cycle signal indicating, when asserted, that the second data processing means can be synchronized with the first data processing means; and wherein each of the first and the second data processing means further comprise: means for generating an instruction clock signal having a period which is a function of a multiple of the period of the unit clock signal; means for generating a request for synchronizing the beginning of the associated instruction clock signal to the beginning of the instruction clock signal of the other data processing means; and means, responsive to the assertion of the first and the second end of cycle signals and also to the operation of the request generating means, for simultaneously synchronizing the beginning of the associated instruction clock signal with a transition of the unit clock signal.

Claim 19

An information processing system comprising: memory means; first data processing means comprising means for addressing the memory means wherein instructions and operands related to instructions are stored; second data processing means comprising means for executing a first plurality of the instructions, the second data processing means being coupled to the memory means for reading therefrom operands associated with certain ones of the first plurality of instructions and for storing within the memory means a result of the certain instructions which operate on the operands; the system further comprising an interface means coupled between the first and the second data processing means, the interface means including a plurality of signals coupled to both the first and the second data processing means, the plurality of signals comprising: a repetitive unit clock signal having a substantially constant period associated therewith, the unit clock signal being received by both the first and the second data processing means; an instruction signal generated by the first data processing means and received by the second data processing means, the instruction signal being expressive of at least which one of the predetermined instructions is to be executed by the second data processing means; a first end of cycle signal asserted by the first data processing means and received by the second data processing means, the first end of cycle signal indicating, when asserted, that the first data processing means can be synchronized with the second data processing means; a second end of cycle signal asserted by the second data processing means and received by the first data processing means, the second end of cycle signal indicating, when asserted, that the second data processing means can be synchronized with the first data processing means; and wherein each of the first and the second data processing means further comprise: means for generating an instruction clock signal having a period which is a function of a multiple of the period of the unit clock signal; means for generating a request for synchronizing the beginning of the associated instruction clock signal to the beginning of the instruction clock signal of the other data processing means; and means, responsive to the assertion of the first and the second end of cycle signals and also to the operation of the request generating means, for simultaneously synchronizing the beginning of the associated instruction clock signal with a transition of the unit clock signal.

Claim 20

An information processing system as set forth in claim 17 wherein the interface means further includes a bidirectional data bus coupled at least to both the first and the second processing means and to the memory means, the first data processing means further comprising an instruction register means for storing an instruction read from the memory means, the instruction register means having an output coupled to the second data processing means by the instruction signal.

Claim 21

An information processing system as set forth in claim 18 wherein the first data processing means comprises instruction decoding means coupled to the output of the instruction register means for decoding predetermined instructions to be executed by the second data processing means, including instructions which operate on operands stored at address locations within the memory means, and wherein the interface means further includes a plurality of address output signals which are coupled from the first data processing means to the second data processing means, the address output signals indicating a byte alignment of an operand within the memory means.

Claim 22

An information processing system as set forth in claim 19 wherein, for a first type of predetermined instruction, the instruction signal includes a first plurality of operand length signals for indicating a number of memory means storage locations occupied by a first operand associated with the first type of predetermined instruction, and wherein the instruction signals further includes a second plurality of operand length signals for indicating a number of memory means storage locations occupied by a second operand associated with the first type of predetermined instruction.

Claim 23

An information processing system as set forth in claim 20 wherein the second data processing means further comprises means responsive to the address output signals and also to the first and the second plurality of operand length signals, for determining a number of memory means access cycles required to access each of the first and the second operands within the memory means, and wherein the interface means further comprises a plurality of signals which are driven by the determining means and which are coupled to the first data processing means for indicating to the first data processing means the determined number of access cycles.

Claim 24

An information processing system as set forth in claim 20 wherein the second data processing means includes a plurality of floating point registers and wherein, for a second type of predetermined instruction, the instruction signal includes a first plurality of signals for indicating a specific one of the floating point registers to be loaded with a first operand associated with the second type of predetermined instruction, and wherein the instruction signal further includes a second plurality of signals for indicating another specific one of the floating point registers associated with the second type of instruction.

Claim 25

An information processing system as set forth in claim 22 wherein the interface means further includes means, responsive to the operation of the executing means of the second data processing means, for generating a plurality of condition code output signals which are coupled to the first data processing means for informing the first data processing means of conditions generated by the execution of one of the first or the second type of predetermined instructions.

Claim 26

An information processing system comprising memory means for storing instructions and operands and having a data bus coupled to a first processing means and to a second processing means, the first and the second processing means being coupled together by an interface means having a plurality of signals, the first processing means comprising means for generating a memory means address and means for generating memory means access cycles for at least reading instructions and operands from the memory means, the first processing means further comprising: means for identifying and providing on the interface means predetermined ones of the instructions to the second processing means for execution therein; means for providing on the interface means a first signal to the second processing means, the first signal indicating a location, relative to an address within the memory means, of an operand associated with a provided instruction, wherein the memory means is comprised of a plurality of bytes; and means for providing on the interface means a second signal to the second processing means, the second signal being expressive of a number of bytes occupied by the operand; the second processing means comprising: means for determining from the first signal and from the second signal a number of memory means access cycles which are required to at least read the operand, the means for determining comprising an output for providing on the interface means a third signal to the first processing means, the third signal being coupled to the memory means access cycles generating means for controlling the operation thereof.

Claim 27

An information processing system comprising memory means for storing instructions and operands and having a data bus coupled to a first processing means and to a second processing means, the first and the second processing means being coupled together by an interface means having a plurality of signals, the first processing means comprising means for generating a memory means address and means for generating memory means access cycles for at least reading instructions and operands from the memory means, the first processing means further comprising: means for identifying and providing on the interface means predetermined ones of the instructions to the second processing means for execution therein; means for providing on the interface means a first signal to the second processing means, the first signal indicating a location, relative to an address within the memory means, of an operand associated with a provided instruction, wherein the memory means is comprised of a plurality of bytes; and means for providing on the interface means a second signal to the second processing means, the second signal being expressive of a number of bytes occupied by the operand; the second processing means comprising: means for determining from the first signal and from the second signal a number of memory means access cycles which are required to at least read the operand, the means for determining comprising an output for providing on the interface means a third signal to the first processing means, the third signal being coupled to the memory means access cycles generating means for controlling the operation thereof.

Claim 28

An information processing system as set forth in claim 24 wherein the interface means further includes a unit clock signal coupled in common to both the first and the second processing means, wherein both the first and the second processing means comprise means for generating an instruction clock signal having a period which is a multiple of the unit clock signal, and wherein both the first and the second processing means further comprise means for synchronizing the beginning of the associated instruction clock signal with a transition of the unit clock signal such that at least the operation of the determining means is synchronized with the operation of the memory means access cycles generating means.

Claim 29

An information processing system as set forth in claim 25 wherein said second processing means further comprises means, coupled to and responsive to the operation of the determining means, for providing a plurality of memory means byte load enable signals to the interface means for selectively activating predetermined bytes of said memory means for storing a result of an instruction therein.

Claim 30

An information processing system as set forth in claim 25 wherein said second processing means further comprises first means for generating condition codes relating to the execution of instructions therein, said condition code generating means having at least one output coupled to said first processing means, and wherein said first processing means further comprises second means for generating condition codes relating to the execution of instructions therein, said first processing means further comprising means for selecting condition codes for examination that are generated by either said first means or generated by said second means.

Claim 31

An information processing system as set forth in claim 27 wherein said instruction identifying means further identifies interlock-type instructions executed by said first processing means which require said second processing means to complete the execution of an instruction before said first processing means executes the interlock-type instruction.

Claim 32

An information processing system as set forth in claim 24 wherein said second processing means further comprises means for determining the occurrence of an exception processing condition related to the execution of instructions therein, said exception processing determining means having an output coupled to said first processing means by said interface means for informing said first processing means of the occurrence of an exception processing condition.

Claim 33

An information processing system as set forth in claim 24 wherein said first processing means further comprises means for indicating a type of further processing to be performed upon the occurrence of an exception processing condition, said means for indicating having at least one output coupled to said second processing means by said interface means.

Claim 34

An information processing system as set forth in claim 24 wherein said second processing means further comprises microinstruction memory means having a plurality of addressable locations for storing microinstructions executed by said second processing means, and wherein said first processing means further comprises means for providing on the interface means a signal for selecting a range of addresses within the microinstruction memory means from which the second processing means executes the microinstructions.

Claim 35

An information processing system as set forth in claim 24 wherein said first processing means further comprises means for indicating to said second processing means that said first processing means has begun execution of an instruction.

Claim 36

An information processing system as set forth in claim 24 wherein said first processing means further comprises means for indicating to said second processing means that said second processing means is to abort an execution of a current instruction so as to cause the second processing means to become idle and also become ready to execute a further instruction while preserving a program state of the second processing means.

Claim 37

Data processing apparatus comprising: memory access control means coupled to a memory means for fetching instructions therefrom, including instructions which operate on operands stored at locations within the memory means; instruction decoding means for identifying at least a first type of instructions which are executed by the data processing apparatus and for identifying at least a second type of instructions which are executed by a second data processing apparatus; means for providing the second type of instructions to the second data processing apparatus; data bus means for providing operands associated with the second type of instructions to the second data processing apparatus; means for providing to the second data processing apparatus information specifying a number of locations within the memory means which are occupied by at least one operand associated with the provided instruction; means for providing to the second data processing apparatus information expressive of a location, relative to an address within the memory means, of the at least one operand; and means, coupled to and responsive to the operation of the second data processing means, and also coupled to a reference clock signal, for synchronizing, with a transition of the reference clock signal, a generation of instruction cycle clocks.

Claim 38

Data processing apparatus comprising: memory access control means coupled to a memory means for fetching instructions therefrom, including instructions which operate on operands stored at locations within the memory means; instruction decoding means for identifying at least a first type of instructions which are executed by the data processing apparatus and for identifying at least a second type of instructions which are executed by a second data processing apparatus; means for providing the second type of instructions to the second data processing apparatus; data bus means for providing operands associated with the second type of instructions to the second data processing apparatus; means for providing to the second data processing apparatus information specifying a number of locations within the memory means which are occupied by at least one operand associated with the provided instruction; means for providing to the second data processing apparatus information expressive of a location, relative to an address within the memory means, of the at least one operand; and means, coupled to and responsive to the operation of the second data processing means, and also coupled to a reference clock signal, for synchronizing, with a transition of the reference clock signal, a generation of instruction cycle clocks.

Claim 39

Data processing apparatus as set forth in claim 34 wherein the first type of instructions include conditional branch instructions and wherein the data processing apparatus further comprises means for selecting for examination either condition codes generated by the data processing apparatus or condition codes generated by the second data processing apparatus.

Claim 40

Data processing apparatus as set forth in claim 35 wherein the synchronizing means is responsive to the operation of the decoding means decoding a conditional branch instruction for suspending the generation of instruction cycle clocks until the second data processing apparatus indicates that it has generated condition codes as a result of the execution of one of the second type of instructions.

Claim 41

Data processing apparatus as set forth in claim 34 and further comprising means for indicating a type of exception processing to be performed upon the occurrence of an exception condition, the indicating means having an output coupled to the second data processing apparatus.

Claim 42

Data processing apparatus as set forth in claim 37 and further comprising means responsive to the operation of the second data processing apparatus for initiating, during the execution of one of the second type of instructions, exception processing.

Claim 43

Data processing apparatus as set forth in claim 37 and further comprising means responsive to the operation of the second data processing apparatus for initiating, subsequent to the execution of one of the second type of instructions, exception processing.

Claim 44

Data processing apparatus as set forth in claim 34 wherein the memory access control means is coupled to and responsive to the operation of the second data processing apparatus for performing a number of memory access cycles which are specified by the second data processing apparatus in order to completely read an operand from the memory means or to completely store a result of an operation within the memory means.

Claim 45

Data processing apparatus as set forth in claim 40 wherein the memory access control means is further coupled to and responsive to the operation of the second data processing apparatus for selectively activating only predetermined bytes of the memory means for storing therein a result of an execution of one of the second type of instructions.

Claim 46

Data processing apparatus as set forth in claim 34 wherein the second type of instructions include instructions having word aligned operands and wherein the memory access control means includes means for determining, prior to the operand being provided on the data bus means, that an operand is not double word aligned; means for reading two consecutive double words each having one word of the operand; and means for double word aligning the operand.

Claim 47

Data processing apparatus coupled during use to memory means, comprising: means for executing instruction stored within the memory means, including floating point and decimal arithmetic instructions, the instructions operating on one or more operands, also stored within the memory means, to produce a result; data bus means, coupled to the memory means, for receiving the operands therefrom and for providing results thereto; first receiving means, for coupling to other data processing apparatus, for receiving an instruction therefrom; second receiving means, for coupling to other data processing apparatus, for receiving information that specifies a number of memory means storage locations which are occupied by at least one operand associated with the instruction; third receiving means, for coupling to other data processing apparatus, for receiving information expressive of a location, relative to an address within the memory means, of the at least on operand; and means, coupled to the second and to the third receiving means, for determining a number of memory means access cycles required to completely read the at least one operand from the memory means.

Claim 48

Data processing apparatus coupled during use to memory means, comprising: means for executing instruction stored within the memory means, including floating point and decimal arithmetic instructions, the instructions operating on one or more operands, also stored within the memory means, to produce a result; data bus means, coupled to the memory means, for receiving the operands therefrom and for providing results thereto; first receiving means, for coupling to other data processing apparatus, for receiving an instruction therefrom; second receiving means, for coupling to other data processing apparatus, for receiving information that specifies a number of memory means storage locations which are occupied by at least one operand associated with the instruction; third receiving means, for coupling to other data processing apparatus, for receiving information expressive of a location, relative to an address within the memory means, of the at least on operand; and means, coupled to the second and to the third receiving means, for determining a number of memory means access cycles required to completely read the at least one operand from the memory means.

Claim 49

Data processing apparatus as set forth in claim 43 and further comprising means, coupled to and responsive to the operation of the determining means, for providing a plurality of memory means byte load enable signals for selectively activating predetermined bytes of the memory means for storing the result of an instruction therein.

Claim 50

Data processing apparatus as set forth in claim 43 and further comprising means for determining the occurrence of an exception processing condition related to the execution of instructions therein, the exception processing determining means having an output for indicating the occurrence of an exception processing condition.

Claim 51

Data processing apparatus as set forth in claim 43 and further comprising microinstruction memory means having a plurality of addressable locations for storing microinstructions executed by the data processing apparatus, the data processing apparatus further comprising an input for receiving an input signal for selecting a range of addresses within the microinstruction memory means from which the data processing apparatus executes the microinstructions.

Claim 52

Data processing apparatus as set forth in claim 43 and further comprising means for generating condition codes relating to the execution of instructions therein, the data processing apparatus further comprising at least one output for outputting the generated condition codes.

Claim 53

Data processing apparatus as set forth in claim 43 and further comprising means, coupled to other data processing apparatus, for receiving a request for synchronization therefrom, and also coupled to a reference clock signal, for synchronizing, with a transition of the reference clock signal, a generation of microinstruction cycle clocks.