Switched current integrator circuit

Claim 2

An integrator circuit for integrating input signals having the form of sampled electrical currents comprising: input means for receiving an input signal and an output for making available an output signal, first and second current memory cells, means for connecting an output of the first current memory cell to an input of the second current memory cell, means for connecting a first output of the second current memory cell to an input of the first current memory cell, means for connecting the input means of the integrator circuit to the input of at least one of the first and second current memory cells, and means for connecting a second output of the second current memory cell to the output of the integrator circuit, wherein the first current memory cell is arranged to produce at its output during a first portion of each sampling period a current related to its input current during a second portion of a preceding sample period and the second current memory cell produces at its outputs during a second portion of each sampling period currents related to the current applied to its input during the first portion of the sampling period, wherein the integrator circuit comprises a further input for receiving a further input signal, the further input being coupled to the input of the first current memory cell during at least the second portion of each sampling period and to the input of the second current memory cell during at least the first portion of each sampling period.

Claim 3

An integrator circuit as claimed in claim 1, wherein the further input is coupled to the first current memory cell via a first switch which is closed only during the second portion of each sampling period and is coupled to the second current memory cell via a second switch which is closed only during the first portion of each sampling period, the first and second portions being non-overlapping.

Claim 4

An integrator circuit as claimed in claim 2, wherein at least one of the first and second current memory cells comprise a current mirror circuit, said current mirror circuit having an input branch comprising a diode connected field effect transistor and an output branch comprising a second field effect transistor, switching means connecting the gate electrodes of the diode connected transistor and the second field effect transistor, and voltage storage means coupled to the second field effect transistor for maintaining a current flow through the second field effect transistor when the switching means is open.

Claim 5

An integrator circuit as claimed in claim 3, wherein the input means comprises first and second input terminals, the first input terminal being connected to the input of the first current memory cell and the second input terminal being connected to the input of the second current memory cell via switching means which is closed only during the first portion of each sampling period.

Claim 6

An integrator circuit as claimed in claim 1, comprising a first current source connected to provide a bias current to the input of the first current memory cell and a second current source connected to provide suitably scaled bias currents to be subtracted from the first and second outputs of the second current memory cell.

Claim 7

An integrator circuit as claimed in claim 1, wherein at least one of the first and second current memory cells comprise a current mirror circuit, said current mirror circuit having an input branch comprising a diode connected field effect transistor and an output branch comprising a second field effect transistor, switching means connecting the gate electrodes of the diode connected transistor and the second field effect transistor, and voltage storage means coupled to the second field effect transistor for maintaining a current flow through the second field effect transistor when the switching means is open.

Claim 8

An integrator circuit as claimed in claim 6, wherein the input means comprise first and second input terminals, the first input terminal being connected to the input of the first current memory cell and the second input terminal being connected to the input of the second current memory cell via switching means which is closed only during the first portion of each sampling period.

Claim 9

An integrator circuit as claimed in claim 1, wherein the input means comprise first and second input terminals, the first input terminal being connected to the input of the first current memory cell and the second input terminal being connected to the input of the second current memory cell via switching means which is closed only during the first portion of each sampling period.

Claim 10

An integrator circuit as claimed in claim 2, wherein the input means comprise first and second input terminals, the first input terminal being connected to the input of the first current memory cell and the second input terminal being connected to the input of the second current memory cell via switching means which is closed only during the first portion of each sampling period.

Claim 11

An integrator circuit as claimed in claim 2, comprising a first current source connected in the integrator circuit so as to provide a bias current to the input of the first current memory cell and a second current source connected in the integrator circuit so as to provide suitably scaled bias currents to be subtracted from the first and second outputs of the second current memory cell.

Claim 12

An integrator circuit as claimed in claim 6, comprising a first current source connected in the integrator circuit so as to provide a bias current to the input of the first current memory cell and a second current source connected in the integrator circuit so as to provide suitably scaled bias currents to be subtracted from the first and second outputs of the second current memory cell.

Claim 13

An integrator circuit as claimed in claim 8, comprising a first current source connected in the integrator circuit so as to provide a bias current to the input of the first current memory cell and a second current source connected in the integrator circuit so as to provide suitably scaled bias currents to be subtracted from the first and second outputs of the second current memory cell.

Claim 14

An integrator circuit for integrating sampled input signal currents comprising: a first current input for receiving a sampled input signal current to be integrated, a current output for the integrated output current, first and second current memory cells each including an input and an output, means coupling the output of the first current memory cell to the input of the second current memory cell, means coupling said output of the second current memory cell to the input of the first current memory cell, means coupling a second output of the second current memory cell to said current output, means coupling the first current input to the input of at least one of said first and second current memory cells, a further current input for receiving a further input signal current, and switching means coupled to said first and second current memory cells and operated by non-overlapping timing signals whereby the first current memory cell produces at its output during a first portion of a sampling period a current related to its input current during a second portion of a preceding sample period and the second memory cell produces at its outputs during a second portion of a sampling period currents related to its input current during the first portion of the sampling period, and whereby the further input is coupled to the input of the first current memory cell during at least the second portion of a sampling period and to the input of the second current memory cell during at least the first portion of a sampling period.

Claim 15

An integrator circuit for integrating sampled input signal currents comprising: a first current input for receiving a sampled input signal current to be integrated, a current output for the integrated output current, first and second current memory cells each including an input and an output, means coupling the output of the first current memory cell to the input of the second current memory cell, means coupling said output of the second current memory cell to the input of the first current memory cell, means coupling a second output of the second current memory cell to said current output, means coupling the first current input to the input of at least one of said first and second current memory cells, a further current input for receiving a further input signal current, and switching means coupled to said first and second current memory cells and operated by non-overlapping timing signals whereby the first current memory cell produces at its output during a first portion of a sampling period a current related to its input current during a second portion of a preceding sample period and the second memory cell produces at its outputs during a second portion of a sampling period currents related to its input current during the first portion of the sampling period, and whereby the further input is coupled to the input of the first current memory cell during at least the second portion of a sampling period and to the input of the second current memory cell during at least the first portion of a sampling period.

Claim 16

An integrator circuit as claimed in claim 13 wherein said switching means comprise: first and second switches coupling said further current input to the inputs of the first and second current memory cells, respectively, said first switch being closed only during the second portion of a sampling period and the second switch being closed only during the first portion of a sampling period, and wherein said timing signals are operative so that the first and second portions of a sampling period are non-overlapping.

Claim 17

An integrator circuit as claimed in claim 14 wherein at least one of said current memory cells comprise a current mirror circuit having an input branch including a diode-connected field effect transistor and an output branch including a second field effect transistor, said switching means including a third switch coupling the gate electrodes of the diode connected and second field effect transistors and operated by said timing signals in synchronism with a respective one of said first and second switches, and a capacitor coupled to the gate electrode of the second field effect transistor.

Claim 18

An integrator circuit as claimed in claim 14, further comprising: a second current input for receiving a second sampled input signal current, said first current input being coupled to the input of the first current memory cell, and said switching means further comprise a third switch coupling the second current input to the input of the second current memory cell and operated by said timing signals to be closed only during said first portion of a sampling period.

Claim 19

An integrator circuit as claimed in claim 16, wherein at least one of said current memory cells comprise a current mirror circuit having an input branch including a diode-connected field effect transistor and an output branch including a second field effect transistor, said switching means including a fourth switch coupling the gate electrodes of the diode-connected and second field effect transistors and operated by said timing signals in synchronism with a respective one of said first and second switches, and a capacitor coupled to the gate electrode of the second field effect transistor.