Circuit arrangement for storing sampled analogue electrical currents

Abstract

Abstract An analogue current memory has a current input (1) which is connected to the input branch of a first current mirror circuit formed by two transistors (T4 and T8). The input and output branches of the first current mirror are isolated by a first switch (S1) which is controlled by a clock signal φA. The output branch of the first current mirror is connected to the input branch of a second current mirror formed by two transistors (T9 and T12). The input and output branches of the second current mirror are isolated by a second switch (S2) which is controlled by a clock signal φB which does not overlap the clock signal φA. The first switch is closed during the first half of the sample period and the second switch is closed during the second half. A current fed to input 1 is mirrored by the transistor T8 while the first switch (S1) is closed and a first capacitor (CA) charges to the gate/source voltage of transistor T8. When the first switch opens the current through transistor T8 is maintained by the charge on the first capacitor. When the second switch (S2) closes the current supplied by transistor (T9) is mirrored onto transistor (T12) and hence to the output (6). When the second switch (S2) opens the current through transistor (T12) is maintained by the charge on a second capacitor (CB). Thus the output is valid when the second switch is open, i.e. during the period φA of the next sample period.

Inventors

• 👤 Neil C. Bird

Bibliographic Details