US4694341A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sample-and-hold circuit
Assignee: Sony Corp
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Filing: 1986-02-04
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Granted: 1987-09-15
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Expires: 2006-02-04
Abstract
Abstract A sample-and-hold circuit is provided wherein an input signal is fed via a first gate element to one end of a first capacitor whose other end is alternately grounded, the one end of the first capacitor being connected via a second capacitor to a gate (or base) of a source (or emitter) follower transistor to obtain an output from the source (or emitter) of the transistor which is connected via a second gate element to one end of the first capacitor, while the gate (or base) of the transistor is connected via a third gate element to a DC voltage supply having a predetermined voltage value, and the second and third gate elements are turned on during a first period of the input signal so that a voltage corresponding to the gate-source (or base-emitter) offset voltage of the transistor is stored in the second capacitor, while the first gate element is turned on during a second period of the input signal to produce an output signal equivalent in level to the input signal.
Inventors
- 👤 Mitsuo Soneda
- 👤 Yoshikazu Hazama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:50
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
275 words
A buffer circuit for translating a periodic input signal comprising; an input terminal supplied with the input signal, first gate means connected to said input terminal and being turned on during a first portion of a period of the input signal, first capacitive means connected to said first gate means; second capacitive means connected to the connection point of said first capacitive means and said first gate means, a source (emitter) follower transistor having a gate (base) connected to said second capacitive means, a source (emitter) and a drain (collector), second gate means connected between the source (emitter) of said source (emitter) follower transistor and said connection point of said first gate means and said first capacitive means, said second gate means being turned on during a second portion of a period of the input signal, third gate means connected to the gate (base) of said source (emitter) follower transistor and being turned on during the second portion of a period of the input signal whereby a the gate-source (base-emitter) offset voltage of said source (emitter) follower transistor is stored across said second capacitive means during the second portion of a period of the input signal, an output terminal led out from the source (emitter) of said source (emitter) follower transistor, said first portion is a trace duration of a horizontal scanning period of the video signal and said second portion is a blanking duration of a horizontal scanning period of the video signal, and wherein said third gate means is connected between the gate (base) of said source (emitter) follower transistor and a voltage source with an average voltage level of said video signal.
Claim 2
Dependent Claim
275 words
A buffer circuit for translating a periodic input signal comprising; an input terminal supplied with the input signal, first gate means connected to said input terminal and being turned on during a first portion of a period of the input signal, first capacitive means connected to said first gate means; second capacitive means connected to the connection point of said first capacitive means and said first gate means, a source (emitter) follower transistor having a gate (base) connected to said second capacitive means, a source (emitter) and a drain (collector), second gate means connected between the source (emitter) of said source (emitter) follower transistor and said connection point of said first gate means and said first capacitive means, said second gate means being turned on during a second portion of a period of the input signal, third gate means connected to the gate (base) of said source (emitter) follower transistor and being turned on during the second portion of a period of the input signal whereby a the gate-source (base-emitter) offset voltage of said source (emitter) follower transistor is stored across said second capacitive means during the second portion of a period of the input signal, an output terminal led out from the source (emitter) of said source (emitter) follower transistor, said first portion is a trace duration of a horizontal scanning period of the video signal and said second portion is a blanking duration of a horizontal scanning period of the video signal, and wherein said third gate means is connected between the gate (base) of said source (emitter) follower transistor and a voltage source with an average voltage level of said video signal.
Claim 3
Dependent Claim
49 words
A buffer circuit according to claim 1, wherein said periodic input signal is a video signal, said first portion is a trace duration of a horizontal scanning period of the video signal and said second portion is a blanking duration of a horizontal scanning period of the video signal.
Claim 4
Dependent Claim
37 words
A buffer circuit according to claim 1, wherein said first gate means is periodically switched during the first portion of a period of said input signal such that the buffer circuit operates as a sampling hold circuit.
Claim 5
Dependent Claim
283 words
A buffer circuit for translating a periodic input signal comprising; an input terminal supplied with the input signal, first gate means connected to said input terminal and being turned on during a first portion of a period of the input signal, first capacitive means connected to said first gate means, second capacitive means connected to the connection point of said first capacitive means and said first gate means, a source (emitter) follower transistor having a gate (base) connected to said second capacitive means, a source (emitter) and a drain (collector), second gate means connected between the source (emitter) of said source (emitter) follower transistor and said connection point of said first gate means and said first capacitive means, said second gate means being turned on during a second portion of a period of the input signal, third gate means connected to the gate (base) of said source (emitter) follower transistor and being turned on during the second portion of a period of the input signal whereby the gate-source (base-emitter) offset voltage of said source (emitter) follower transistor is stored across said second capacitive means during the second portion of a period of the input signal, an output terminal led out from the source (emitter) of said source (emitter) follower transistor, and further comprising a fourth gate means which is turned on during the second portion of a period of said input signal, third capacitive means connected between said fourth gate means and the connection point of the said first gate means and said first capacitive means, and a transistor having a gate connected to said fourth gate means, source connected to the drain (collector) of said source (emitter) follower transistor and a drain.
Claim 6
Dependent Claim
283 words
A buffer circuit for translating a periodic input signal comprising; an input terminal supplied with the input signal, first gate means connected to said input terminal and being turned on during a first portion of a period of the input signal, first capacitive means connected to said first gate means, second capacitive means connected to the connection point of said first capacitive means and said first gate means, a source (emitter) follower transistor having a gate (base) connected to said second capacitive means, a source (emitter) and a drain (collector), second gate means connected between the source (emitter) of said source (emitter) follower transistor and said connection point of said first gate means and said first capacitive means, said second gate means being turned on during a second portion of a period of the input signal, third gate means connected to the gate (base) of said source (emitter) follower transistor and being turned on during the second portion of a period of the input signal whereby the gate-source (base-emitter) offset voltage of said source (emitter) follower transistor is stored across said second capacitive means during the second portion of a period of the input signal, an output terminal led out from the source (emitter) of said source (emitter) follower transistor, and further comprising a fourth gate means which is turned on during the second portion of a period of said input signal, third capacitive means connected between said fourth gate means and the connection point of the said first gate means and said first capacitive means, and a transistor having a gate connected to said fourth gate means, source connected to the drain (collector) of said source (emitter) follower transistor and a drain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-14 | 1991-03-16 | 1991-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-14 | 1995-03-16 | 1995-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-14 | 1999-03-16 | 1999-09-15 | $7700.00 | Window Closed / Lapsed |