Circuit arrangement for processing sampled analogue electrical signals

Claim 1

A circuit arrangement for processing sampled analogue electrical current signals, comprising: means for combining, in predetermined proportions, an input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and means for deriving a processed output signal from a combined current produced by the combining means in successive sample periods, at least one current mirror circuit arrangement which comprises an input connected to an input circuit branch of a first current mirror circuit and an output connected to an output circuit branch of the first current mirror circuit, wherein the input circuit branch comprises a series arrangement of first and second MOS transistors, the output circuit branch comprises a series arrangement of third and fourth MOS transistors, gate electrodes of the first and third transistors being connected together and to a bias source, gate electrodes of the second and fourth transistors being connected together and to the input, wherein the bias source comprises means for generating a bias current equal to the input current, the bias current generating means comprising a further output branch of the first current mirror circuit, means for applying the bias current to a diode connected transistor, and means for connecting the drain electrode of the diode connected transistor to the gate electrodes of the first and third transistors, wherein a gate width to length ratio of the diode connected transistor and the current through the diode connected transistor are selected so that a voltage of V t +2V on is produced across the diode connected transistor, where V t is the threshold voltage and V on is the saturation voltage.