US4412186A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror circuit
Assignee: Toshiba Corp
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Filing: 1981-04-06
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Granted: 1983-10-25
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Expires: 2001-04-06
Abstract
Abstract A current mirror circuit having high accuracy in its current mirror transfer ratio λ even when constructed of P-N-P transistors. The circuit includes two stages each having three transistors of one conductivity type and a fourth transistor of a different conductivity type. Two of the like transistors of each stage have a common base electrode and the third like transistor is connected between the common electrode and a reference potential. The fourth transistor of each stage has its base connected to an individual one of the collectors of the base-connected transistors and its emitter connected both to a current source and the base of the third like transistor. The emitters of the base-connected transistors of the first stage and the collectors of the fourth transistors of each stage are connected to a power supply. The emitters of the base-connected transistors of the second stage are connected to the collectors of the base-connected transistors of the first stage. The collector of one of the base-connected transistors of the second stage is connected to a current source as an input and the collector of the other base-connected transistor of the second stage is connected to a load as the output.
Inventors
- 👤 Katsumi Nagano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:15
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
314 words
A current mirror circuit comprising: a power supply terminal; an input current source; an output across a load; a first stage including: first, second and third transistors of a first conductivity type, each having a base, a collector and an emitter electrode, said first and second transistors having their base electrodes connected in common and their emitter electrodes connected to said power supply terminal, and said third transistor having its emitter connected in common with said base electrodes of said first and second transistors and its collector electrode connected to a reference voltage; a fourth transistor of a second conductivity type, having a base electrode connected to said collector electrode of said second transistor, a collector electrode connected to said power supply terminal, and an emitter electrode connected to the base electrode of said third transistor; and a current source connected to said emitter electrode of said fourth transistor; a second stage including: fifth, sixth and seventh transistors of said first conductivity type, each having a base, a collector and an emitter electrode, said fifth and sixth transistors having their base electrodes connected in common and their emitter electrodes connected to the respective collector electrodes of said first and second transistors, the collector electrode of said fifth transistor being connected to said input current source, and the collector electrode of said sixth transistor being connected to said output, and said seventh transistor having its emitter electrode connected in common with the base electrodes of said fifth and sixth transistors and its collector electrode connected to said reference voltage; an eighth transistor of said second conductivity type having a base electrode connected to the collector electrode of said fifth transistor, a collector electrode connected to said power supply terminal, and an emitter electrode connected to the base electrode of said seventh transistor; and a current source connected to the emitter electrode of said seventh transistor.
Claim 2
Dependent Claim
314 words
A current mirror circuit comprising: a power supply terminal; an input current source; an output across a load; a first stage including: first, second and third transistors of a first conductivity type, each having a base, a collector and an emitter electrode, said first and second transistors having their base electrodes connected in common and their emitter electrodes connected to said power supply terminal, and said third transistor having its emitter connected in common with said base electrodes of said first and second transistors and its collector electrode connected to a reference voltage; a fourth transistor of a second conductivity type, having a base electrode connected to said collector electrode of said second transistor, a collector electrode connected to said power supply terminal, and an emitter electrode connected to the base electrode of said third transistor; and a current source connected to said emitter electrode of said fourth transistor; a second stage including: fifth, sixth and seventh transistors of said first conductivity type, each having a base, a collector and an emitter electrode, said fifth and sixth transistors having their base electrodes connected in common and their emitter electrodes connected to the respective collector electrodes of said first and second transistors, the collector electrode of said fifth transistor being connected to said input current source, and the collector electrode of said sixth transistor being connected to said output, and said seventh transistor having its emitter electrode connected in common with the base electrodes of said fifth and sixth transistors and its collector electrode connected to said reference voltage; an eighth transistor of said second conductivity type having a base electrode connected to the collector electrode of said fifth transistor, a collector electrode connected to said power supply terminal, and an emitter electrode connected to the base electrode of said seventh transistor; and a current source connected to the emitter electrode of said seventh transistor.
Claim 3
Dependent Claim
20 words
The current mirror circuit of claim 1 wherein the transistors of the first conductivity type are of the PNP type.
References Cited (Backward Citations)
US3936725A
Cited
US4166971A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-24 | 1987-04-25 | 1987-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-24 | 1991-04-25 | 1991-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-24 | 1995-04-25 | 1995-10-25 | $7700.00 | Window Closed / Lapsed |