Linear amplifier

Claim 2

A linear amplifier comprising an MOS transistor amplifying stage having a signal input and a signal output circuit, a load circuit connected in the signal output circuit, comprising first and second MOS transistors connected in cascode, and compensation means for biasing the gate electrodes of the first and second transistors in response to the voltage across the cascode connection in a sense so as to maintain the apparent differential resistance of the cascode connection.

Claim 3

An amplifier as claimed in claim 1, wherein the first and second MOS transistors are depletion mode, n-channel transistors.

Claim 4

An amplifier as claimed in claim 2, wherein the compensation means comprises an enhancement mode MOS transistor and a depletion mode MOS transistor with the gates thereof connected together and coupled to the gates of the first and second transistors, and means connecting the drain of the enhancement transistor to the source of the depletion transistor and to its own gate.

Claim 5

A linear amplifier comprising, a transistor amplifying stage including at least one MOS transistor and having a signal input and a signal output, a bias voltage supply terminal, a load circuit coupled between said signal output and said supply terminal, said load circuit including first and second depletion mode MOS transistors of the same conductivity type with one end of the source-drain path of the first MOS transistor coupled to said signal output and the source-drain path of the second MOS transistor coupled to the other end of the source-drain path of the first transistor, and a compensating circuit coupled to gate electrodes of the first and second transistors, said compensating circuit including means for supplying a voltage to the gate electrode of the first transistor so as to counter the normal decrease in threshold voltage of said first transistor for an increase in its source-to-substrate voltage thereby maintaining the resistance value of the load circuit.

Claim 6

A linear amplifier comprising, a transistor amplifying stage including at least one MOS transistor and having a signal input and a signal output, a bias voltage supply terminal, a load circuit coupled between said signal output and said supply terminal, said load circuit including first and second depletion mode MOS transistors of the same conductivity type with one end of the source-drain path of the first MOS transistor coupled to said signal output and the source-drain path of the second MOS transistor coupled to the other end of the source-drain path of the first transistor, and a compensating circuit coupled to gate electrodes of the first and second transistors, said compensating circuit including means for supplying a voltage to the gate electrode of the first transistor so as to counter the normal decrease in threshold voltage of said first transistor for an increase in its source-to-substrate voltage thereby maintaining the resistance value of the load circuit.

Claim 7

A linear amplifier as claimed in claim 4 wherein said compensating circuit comprises an enhancement mode MOS transistor and a depletion mode MOS transistor of the same conductivity type having their source-drain paths connected in series, one end of the source-drain path of said enhancement transistor being connected to said signal output, and means connecting the gates of said transistors together, to said gates of said first and second transistors and to a drain-source connection between said enhancement and depletion transistors.

Claim 8

A linear amplifier as claimed in claim 5 wherein said enhancement transistor has a large W/L ratio and said depletion transistor has a small W/L ratio.

Claim 9

A linear amplifier as claimed in claims 4, 5 or 6 wherein all said transistors are of the same conductivity type.

Claim 10

A linear amplifier comprising, a transistor amplifying stage including at least one MOS transistor and having a signal input and a signal output, a bias voltage supply terminal, a load circuit coupled between said signal output and said supply terminal, said load circuit including a first depletion mode MOS transistor having a source-drain path coupled between said signal output and said bias voltage supply terminal, an enhancement mode MOS transistor having one end of its source-drain path coupled to said signal output and a second depletion mode MOS transistor having one end of its source-drain path coupled to the other end of the source-drain path of said enhancement transistor and the other end of its source-drain path coupled to said supply terminal, and means coupling the gates of said first and second depletion mode transistors and said enhancement mode transistor together and to a junction of the source-drain paths of said enhancement mode and said second depletion mode transistors, and wherein the transistors of said load circuit are of the same conductivity type.

Claim 11

A linear amplifier comprising, a transistor amplifying stage including at least one MOS transistor and having a signal input and a signal output, a bias voltage supply terminal, a load circuit coupled between said signal output and said supply terminal, said load circuit including a first depletion mode MOS transistor having a source-drain path coupled between said signal output and said bias voltage supply terminal, an enhancement mode MOS transistor having one end of its source-drain path coupled to said signal output and a second depletion mode MOS transistor having one end of its source-drain path coupled to the other end of the source-drain path of said enhancement transistor and the other end of its source-drain path coupled to said supply terminal, and means coupling the gates of said first and second depletion mode transistors and said enhancement mode transistor together and to a junction of the source-drain paths of said enhancement mode and said second depletion mode transistors, and wherein the transistors of said load circuit are of the same conductivity type.

Claim 12

A linear amplifier comprising an MOS transistor amplifying stage that includes at least first and second MOS transistors connected in a long-tail pair circuit configuration having first and second legs connected to a common current supply circuit, a bias voltage supply terminal, the first leg including the first MOS transistor which has a signal output circuit coupled to said supply terminal via a first load circuit and the second leg including the second MOS transistor which has a signal output circuit coupled to said supply terminal via a second load circuit, first and second signal input terminals coupled to input electrodes of said first and second MOS transistors, respectively, each of said load circuits including third and fourth depletion mode MOS transistors of the same conductivity type connected in cascode between said supply terminal and the associated signal output circuit of the respective first or second MOS transistor of the long-tail pair circuit, and a compensating circuit coupled to gate electrodes of the third and fourth transistors, said compensating circuit including means for supplying a voltage to the gate electrode of the third transistor so as to counter the normal decrease in threshold voltage of said third transistor for an increase in its source-to-substrate voltage thereby maintaining the resistance value of the load circuit.

Claim 13

A linear amplifier comprising an MOS transistor amplifying stage that includes at least first and second MOS transistors connected in a long-tail pair circuit configuration having first and second legs connected to a common current supply circuit, a bias voltage supply terminal, the first leg including the first MOS transistor which has a signal output circuit coupled to said supply terminal via a first load circuit and the second leg including the second MOS transistor which has a signal output circuit coupled to said supply terminal via a second load circuit, first and second signal input terminals coupled to input electrodes of said first and second MOS transistors, respectively, each of said load circuits including third and fourth depletion mode MOS transistors of the same conductivity type connected in cascode between said supply terminal and the associated signal output circuit of the respective first or second MOS transistor of the long-tail pair circuit, and a compensating circuit coupled to gate electrodes of the third and fourth transistors, said compensating circuit including means for supplying a voltage to the gate electrode of the third transistor so as to counter the normal decrease in threshold voltage of said third transistor for an increase in its source-to-substrate voltage thereby maintaining the resistance value of the load circuit.

Claim 14

An amplifier as claimed in claim 9, wherein the long-tail-pair circuit includes a common mode feedback system.

Claim 15

An amplifier as claimed in claim 9 further comprising means connecting wherein the signal output circuits of the first and second MOS transistors to a circuit for combining their outputs to form a single low voltage output.