High speed integrator for data recovery and a costas phase-locked-loop circuit incorporating same

Claim 2

An integrate circuit comprising: a first stage, a differential transistor input stage, which first stage has complementary outputs and includes a switch means to enable and disable the same to set a period of time during which integration shall be performed; a second stage, a signal store and integrate stage, which second stage includes: a pair of like transistors, these being arranged in parallel, the control electrodes of which transistors are connected to respective complementary outputs of said first-stage; a pair of current sources connected respectively to said transistors, and, a capacitor, connected between said pair of transistors, across said pair of current sources; and, a third stage, a differential transistor output stage, the inputs to which third stage are connected to each side respectively of said capacitor, which third stage includes a switch means to enable and disable the same to set a consecutive period of time during which the voltage across said capacitor is read and an output signal produced in response thereto.

Claim 3

An integrate circuit, as claimed in claim 1, wherein this circuit includes switch control means, co-operative with the switch means of both said first and second stages to determine successive periods of integration and reading of voltage across said capacitor respectively, it being arranged that said capacitor is reset by said pair of current sources whilst the first stage is disabled, and, said reading of voltage is performed at or near the onset of this reset.

Claim 4

An integrate circuit as claimed in claim 1, which circuit also includes: a switch means, part of said second stage, interposed between said pair of current sources and said transistors, and included below said capacitor, the switch means of said second stage being ganged to the switch means of said first stage to operate simultaneously therewith; a further pair of current sources parallel to the pair first mentioned, and provided to reset said capacitor; and, a further switch means, interposed between said further pair of current sources and said transistors, to set a period of time for resetting said capacitor.

Claim 5

An integrate circuit, as claimed in claim 3, wherein this circuit includes switch control means co-operative with the switch means of said first and second stages, the switch means of said third stage and said further switch means, to determine successive periods of integration and hold, and consecutive periods of reading of voltage across, and resetting, said capacitor respectively.

Claim 6

An integrate circuit, as claimed in claim 1, wherein all said transistors, said current sources and said switch means are implemented using npn type transistors, all incorporated in a common integrated circuit.

Claim 7

An integrate circuit, as claimed in claim 1, including: current modulation means arranged to modulate the currents of said pair of current sources first mentioned; and, signal rectification means, co-operative with said modulation means arranged for receiving an input signal applied to said first stage.

Claim 8

A combination of plurality of like integrate circuits, each said integrate circuit comprising: a first stage, a differential transistor input stage, which first stage has complementary outputs and includes a switch means to enable and disable the same to set a period of time during which integration shall be performed; a second stage, a signal store and integrate stage, which second stage includes: a pair of like transistors, these being arranged in parallel, the control electrodes of which transistors are connected to respective complementary outputs of said first-stage; a pair of current sources connected respectively to said transistors, and, a capacitor, connected between said pair of transistors, across said pair of current sources; and, a third stage, a differential transistor output stage, the inputs to which third stage are connected to each side respectively of said capacitor, which third stage includes a switch means to enable and disable the same to set a consecutive period of time during which the voltage across said capacitor is read and an output signal produced in response thereto; wherein coupling is provided at input of each said integrate circuit such that each shall receive input signal in parallel; together with: switch control means, co-operative with all said switch means of said plurality of like integrate circuits, to operate said like integrate circuits in a phase sequential manner.

Claim 9

A combination of plurality of like integrate circuits, each said integrate circuit comprising: a first stage, a differential transistor input stage, which first stage has complementary outputs and includes a switch means to enable and disable the same to set a period of time during which integration shall be performed; a second stage, a signal store and integrate stage, which second stage includes: a pair of like transistors, these being arranged in parallel, the control electrodes of which transistors are connected to respective complementary outputs of said first-stage; a pair of current sources connected respectively to said transistors, and, a capacitor, connected between said pair of transistors, across said pair of current sources; and, a third stage, a differential transistor output stage, the inputs to which third stage are connected to each side respectively of said capacitor, which third stage includes a switch means to enable and disable the same to set a consecutive period of time during which the voltage across said capacitor is read and an output signal produced in response thereto; wherein coupling is provided at input of each said integrate circuit such that each shall receive input signal in parallel; together with: switch control means, co-operative with all said switch means of said plurality of like integrate circuits, to operate said like integrate circuits in a phase sequential manner.

Claim 10

The combination, as claimed in claim 7, further comprising a common differential output load connected to the third stage of each said like integrate circuit.

Claim 11

A pair of like integrate circuits, first and second integrate circuits respectively, each of which circuits comprises: a first stage, a differential transistor input stage, which first stage has a complementary outputs and includes a switch means to enable and disable the same to set a period of time during which integration shall be performed; a second stage, a signal store and integrate stage, which second stage includes: a pair of like transistors, these being arranged in parallel, the control electrodes of which transistors are connected to respective complementary outputs of said first-stage; a pair of current sources connected respectively to said transistors, and, a capacitor, connected between said pair of transistors, across said pair of current sources; and, a third stage, a differential transistor output stage, the inputs to which third stage are connected to each side respectively of said capacitor, which third stage includes a switch means to enable and disable the same to set a consecutive period of time during which the voltage across said capacitor is read and an output signal produced in response thereto; wherein the switch means of each first stage of said first and second integrate circuits are ganged to the switch means of the third stage of said second and first integrate circuits, respectively; wherein said pair of current sources of each said first and second integrate circuits consist in a common pair of current sources; together with: switch control means arranged to provide antiphase switch control signals to the switch means ganged as aforesaid; and, a common differential output load connected to the third stage of both of said pair of like integrate circuits.

Claim 12

A pair of like integrate circuits, first and second integrate circuits respectively, each of which circuits comprises: a first stage, a differential transistor input stage, which first stage has a complementary outputs and includes a switch means to enable and disable the same to set a period of time during which integration shall be performed; a second stage, a signal store and integrate stage, which second stage includes: a pair of like transistors, these being arranged in parallel, the control electrodes of which transistors are connected to respective complementary outputs of said first-stage; a pair of current sources connected respectively to said transistors, and, a capacitor, connected between said pair of transistors, across said pair of current sources; and, a third stage, a differential transistor output stage, the inputs to which third stage are connected to each side respectively of said capacitor, which third stage includes a switch means to enable and disable the same to set a consecutive period of time during which the voltage across said capacitor is read and an output signal produced in response thereto; wherein the switch means of each first stage of said first and second integrate circuits are ganged to the switch means of the third stage of said second and first integrate circuits, respectively; wherein said pair of current sources of each said first and second integrate circuits consist in a common pair of current sources; together with: switch control means arranged to provide antiphase switch control signals to the switch means ganged as aforesaid; and, a common differential output load connected to the third stage of both of said pair of like integrate circuits.

Claim 13

A Costas phase-locked-loop circuit comprising: first and second dual integrate circuits; a first mixer connected to the outputs of said first and second dual integrate circuits; a voltage controlled oscillator responsive to the output of said first mixer; second and third mixers, responsive to a common input signal, referenced in quadrature to said oscillator; and connected each at output to the first and second dual circuits; and, phase clock and reset timing means, responsive to said oscillator, co-operative with each dual circuit and providing the switch control means therefor; wherein each said first and second dual integrate circuit comprises: a pair of like integrate circuits, first and second integrate circuits respectively, each of which circuits comprises: a first stage, a differential transistor input stage, which first stage has complementary outputs and includes a switch means to enable and disable the same to set a period of time during which integration shall be performed; a second stage, a signal store and integrate stage, which second stage includes: a pair of like transistors, these being arranged in parallel, the control electrodes of which transistors are connected to respective complementary outputs of said first-stage; a pair of current sources connected respectively to said trasistors, and, a capacitor, connected between said pair of transistors, across said pair of current sources; and, a third stage, a differential transistor output stage, the inputs to which third stage are connected to each side respectively of said capacitor, which third stage includes a switch means to enable and disable the same to set a consecutive period of time during which the voltage across said capacitor is read and an output signal produced in response thereto; wherein the switch means of each first stage of said first and second integrate circuits are ganged to the switch means of the third stage of said second and first integrate circuits, respectively; wherein said pair of current sources of each said first and second integrate circuits consist in a common pair of current sources; together with: switch control means arranged to provide antiphase switch control signals to the switch means ganged as aforesaid; and, a common differential output load connected to the third stage of both of said pair of like integrate circuits.

Claim 14

A Costas phase-locked-loop circuit comprising: first and second dual integrate circuits; a first mixer connected to the outputs of said first and second dual integrate circuits; a voltage controlled oscillator responsive to the output of said first mixer; second and third mixers, responsive to a common input signal, referenced in quadrature to said oscillator; and connected each at output to the first and second dual circuits; and, phase clock and reset timing means, responsive to said oscillator, co-operative with each dual circuit and providing the switch control means therefor; wherein each said first and second dual integrate circuit comprises: a pair of like integrate circuits, first and second integrate circuits respectively, each of which circuits comprises: a first stage, a differential transistor input stage, which first stage has complementary outputs and includes a switch means to enable and disable the same to set a period of time during which integration shall be performed; a second stage, a signal store and integrate stage, which second stage includes: a pair of like transistors, these being arranged in parallel, the control electrodes of which transistors are connected to respective complementary outputs of said first-stage; a pair of current sources connected respectively to said trasistors, and, a capacitor, connected between said pair of transistors, across said pair of current sources; and, a third stage, a differential transistor output stage, the inputs to which third stage are connected to each side respectively of said capacitor, which third stage includes a switch means to enable and disable the same to set a consecutive period of time during which the voltage across said capacitor is read and an output signal produced in response thereto; wherein the switch means of each first stage of said first and second integrate circuits are ganged to the switch means of the third stage of said second and first integrate circuits, respectively; wherein said pair of current sources of each said first and second integrate circuits consist in a common pair of current sources; together with: switch control means arranged to provide antiphase switch control signals to the switch means ganged as aforesaid; and, a common differential output load connected to the third stage of both of said pair of like integrate circuits.