US3839679A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed gated video integrator with zero offset
Assignee: United States Department of the Navy
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Filing: 1973-06-21
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Granted: 1974-10-01
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Expires: 1993-06-21
Abstract
Abstract A high speed gated video integrator having double differential amplifiers wherein equal currents bias ''''on'''' one side of each differential amplifier. Then, to perform integration, the differential amplifiers are gated, and integration occurs only during such gated period. Low level pulses, independent of polarity and amplitude, can be integrated.
Inventors
- 👤 R Hughes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:11
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/06; H03K4/08; H03K4/48; H03K4/50; G; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; H03K5/00; H03K5/01; H03K5/02
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
208 words
An electronic integrator circuit, comprising: an input for receiving an unknown electrical pulse; at least one differential amplifier pair wherein each differential amplifier of said pair has first and second transistors with common connected first terminals providing first and second current paths through said differential amplifier; a separate constant current source attached to each said differential amplifier including at least one transistor having its first terminal coupled to a bias voltage source, its second terminal coupled to said common connected first terminals of its respective differential amplifier and its third terminal coupled to said input wherein the current value provided by the current sources is controlled by the electrical signal received by said input; means for storing an electrical charge coupled to the second terminal of the second transistor of each differential amplifier; wherein the second terminal of said first transistor of each said differential amplifier is connected to circuit common ground; and meanS coupled to the third terminal of the first transistor of each said differential amplifier for selectively controlling the current path within said differential amplifiers by simultaneously rendering each said first transistor nonconductive; wherein the charge on the storing means is responsive to the current provided by the current sources through said second current paths.
Claim 2
Dependent Claim
208 words
An electronic integrator circuit, comprising: an input for receiving an unknown electrical pulse; at least one differential amplifier pair wherein each differential amplifier of said pair has first and second transistors with common connected first terminals providing first and second current paths through said differential amplifier; a separate constant current source attached to each said differential amplifier including at least one transistor having its first terminal coupled to a bias voltage source, its second terminal coupled to said common connected first terminals of its respective differential amplifier and its third terminal coupled to said input wherein the current value provided by the current sources is controlled by the electrical signal received by said input; means for storing an electrical charge coupled to the second terminal of the second transistor of each differential amplifier; wherein the second terminal of said first transistor of each said differential amplifier is connected to circuit common ground; and meanS coupled to the third terminal of the first transistor of each said differential amplifier for selectively controlling the current path within said differential amplifiers by simultaneously rendering each said first transistor nonconductive; wherein the charge on the storing means is responsive to the current provided by the current sources through said second current paths.
Claim 3
Dependent Claim
35 words
The circuit of claim 1 wherein said current path controlling means is responsive to a controllable electrical pulse source, and said first transistor of each differential amplifier is driven non-conductive by an appropriate electrical pulse.
Claim 4
Dependent Claim
53 words
The circuit of claim 2 wherein the electrical pulses from said controllable pulse source are simultaneously coupled to the first transistor of each differential amplifier, such that the charge on said storage device is responsive to the pulse at said receiving input during the period said pulses are applied to said first transistors.
Claim 5
Dependent Claim
46 words
The circuit of claim 3 wherein said current sources are single transistor circuits wherein the transistor has emitter, collector, and base terminals with the base of the transistor connected to said receiving input and the collector connected to the junction of said common connected first terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-30 | 1978-04-01 | 1978-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-30 | 1982-04-01 | 1982-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-30 | 1986-04-01 | 1986-10-01 | $7700.00 | Window Closed / Lapsed |