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Patent US5056084A successfully refreshed from Google Patents.
US5056084A
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System for transmitting hdlc frames on a pcm type link using a single hdlc circuit and a transposition buffer memory
Assignee: Alcatel CIT SA
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Filing: 1989-12-29
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Granted: 1991-10-08
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Expires: 2009-12-29
Abstract
Abstract A system for transmitting HDLC frames on a PCM type link uses a single HDLC circuit and a transposition buffer memory to provide a compact system by economizing on the number of components, enabling operation at high speed without risk of starvation on the PCM link. The system uses a single transposition buffer memory with a read cycle distinct from the write cycle cooperating with a single single-channel HDLC frame formatting circuit. The memory is written with the formatted HDLC frames and read under the control of means for selective sampling in the memory of data for building successive blocks of interleaved channels of the PCM frame.
Inventors
- 👤 Noel Le Corre
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:18
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/16; H04L; H04L9/00; H04L9/40
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
104 words
System for transmitting HDLC frames on a multi-channel PCM type link, the system comprising HDLC frame building first means for each transmission channel feeding second means for inserting the HDLC frames in a time-division multiplexing PCM format, wherein said first and second means are constituted by a single transposition buffer memory with a read cycle distinct from the write cycle cooperating with a single single-channel HDLC frame formatting circuit, said memory being written with said formatted HDLC frames and read under the control of means for selective sampling in said memory of data for building successive blocks of interleaved channels of said PCM frame.
Claim 2
Dependent Claim
104 words
System for transmitting HDLC frames on a multi-channel PCM type link, the system comprising HDLC frame building first means for each transmission channel feeding second means for inserting the HDLC frames in a time-division multiplexing PCM format, wherein said first and second means are constituted by a single transposition buffer memory with a read cycle distinct from the write cycle cooperating with a single single-channel HDLC frame formatting circuit, said memory being written with said formatted HDLC frames and read under the control of means for selective sampling in said memory of data for building successive blocks of interleaved channels of said PCM frame.
Claim 3
Dependent Claim
27 words
System according to claim 1 wherein said buffer memory comprises at least N circular FIFO type memory segments corresponding to N channels routed onto said PCM link.
Claim 4
Dependent Claim
31 words
System according to claim 2 wherein each of said memory segments comprises a respective write pointer and in that said memory comprises a single read pointer for all said memory segments.
Claim 5
Dependent Claim
43 words
System according to claim 1 wherein said buffer memory includes write and read pointers and said system further including a circuit for selectively feeding said HDLC circuit comprising a microprocessor receiving data supplied by said write and read pointers of said buffer memory.
Claim 6
Dependent Claim
26 words
System according to claim 4 wherein said microprocessor of said circuit for selectively feeding said HDLC circuit cooperates with a local memory for temporary data storage.
Claim 7
Dependent Claim
53 words
System according to claim 4 wherein said microprocessor comprises a logic circuit for selectively feeding said HDLC circuit with data whereby priority is given to filling a least full segment of said buffer memory at least when the quantity of data in said memory least full segment is lower than a predetermined threshold.
Claim 8
Dependent Claim
47 words
System according to claim 4 wherein said microprocessor of said circuit for selectively feeding said HDLC circuit and said single HDLC circuit cooperate according to a master/slave relation through a bus the data signalling rate of which is determined by acknowledgements sent by said single HDLC circuit.
Claim 9
Dependent Claim
19 words
System according to claim 4 wherein said selective feed circuit supplies data byte by byte to said HDLC circuit.
Claim 10
Dependent Claim
32 words
System according to claim 8 wherein said microprocessor of said selective feed circuit supplies said data bytes to said HDLC circuit accompanied by data identifying the current, frame end and synchronization bytes.
Claim 11
Dependent Claim
14 words
System according to claim 1 comprising means for de-activating and bypassing said HDLC circuit.
Claim 12
Dependent Claim
25 words
System according to claim 10 wherein said de-activating and bypassing means are activated for loading synchronization bytes of each PCM frame into said buffer memory.
Claim 13
Dependent Claim
36 words
System according to claim 1 comprising means for masking clock signals controlling said HDLC circuit and/or means for sequencing writing in said buffer memory in case of data starvation in the feed to said HDLC circuit.
Claim 14
Dependent Claim
21 words
System according to claim 1 wherein said memory is accessed by four-period cycles comprising a read period and three write periods.
References Cited (Backward Citations)
FR2516730A1
Cited
US4542498A
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EP0100092A2
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |