Multiple communication interface between processor and digital transmission means

Claim 2

A multiple communication interface between processor and digital transmission means, such as a 32-channel 64 kbit/s PCM group belonging to a data communications system, which operates as a processor peripheral unit, which is able to control the group channels as communication bidirectional paths between the processor and other nodes of the system, each path being usable for the exchange of data organized into messages according to dialogue procedures of the high level type, and which comprises: - a first plurality of circuits (LVI),for the simultaneous processing of incoming channels; - a second plurality of circuits(LVO),for generating the outgoing channels; - a third plurality of circuits (BTT), for the temporaneous storage of the information arriving from said first ensemble of circuits and the transfer of information arriving from a microprogrammed logic unit (LMT), towards said second circuit plurality; - a fourth plurality of circuit (DSC) for message storage and the exchange of information with the processor; - a fast microprogrammed logic unit (LMT), able to control allocation in the memory of incoming and outgoing messages to transfer in real time the data from the memory to transmitting circuits and from the receiving circuits to the memory, to count the significant bits of each received or transmitted message, to ; check the compatibility of the number 6f bits of each message with the rules of the used dialogue procedure, to signal the processor the occurred reception of the messages, the events on the communications paths and their transitions, to interpret and carry out the commands coming from the processor, such as the transmission order of a message, enabling and inhibiting of the communications paths, transition on communications paths, requests of availably of a memory area into which to load a message to transmit, filtering and generation of stuffing messages.

Claim 3

A multiple communication interface as in claim I, characterized in that said first plurality of circuits (LVI) comprises: - a single operative logic circuit (PPR, LTC, SBV, SOV, DUP, EXO) for all the channels, which realizes in an independent way, for each of them, the algorithms of the dialogue procedure for the incoming bit flow of the PCM group to the levels of recognition of the beginning and end of the messages, of aborted message, of the idle or active state of the channel, of the validity of the message, of the correctness of cyclical redundancies, of the elimination of the stuffing bits, of the assembling into octets of the received data, and of the recognition of the length of the residual character, which operates in time sharing on the successive channels of the group, causing for each of them the evolution of an internal state consisting ofabitsequence comprising for each incoming channel the last 8-bits received, the partial result of the check computation of cyclical redundancies, and all information relating to the preceding events on the channel which are significant for the algorithm of the procedure; as well as the bit in reception over PCM group, which effects operations which are only function of the bit sequence instantaneously applied to its inputs and contains means apt to decode the states corresponding to events to be signalled to the rest of the interface; - some registers (RPS, SCO, SOC) apt to contain the bit sequence forming the instantaneous state of an incoming channel, which can be re-written with the results supplied by the operative logic circuit at the rhythm of bit reception on PCM group; - some means (CVI, CV2) apt to replace in said registers in synchronism with the incoming channels, the bit sequence relating to the instantaneous state of the ending channel with the analogous sequence relating to the beginning channel; - some means (SVS, SVO, SVC), apt to store the instantaneous states of non-current channels without requiring any read and write addressing as they are based on the cyclical shift of the information in synchronism with the incoming PCM group.

Claim 4

Multiple communication interface, as in claim 1, characterized in that said second plurality of circuits (LVO) comprises: - single operative logic circuit (LTT, PPT, SUC, MSB, SBT, DUO, EXT) for all the channels, apt to act on a bit sequence forming the instantaneous internal state of an outgoing channel, said sequence consisting of an octet of transmission data,of the code of the last command received by the rest of the interface, of the partial result of the computation of the cyclical redundancies, of a state code comprising the information corresponding to the previous events on the channel, and to realize for said sequence the algorithms of the dialogue procedure by generating at each time slot of the outgoing PCM group the logic value of the bit to be transmitted and the new instantaneous state of the channel, to work in time sharing on the subsequent group channels by executing for each of them the operations of beginning and end of the messages, of possible transmission of the criterion of aborted message, of request to the rest of the interface of the octet to be transmitted, of recognition of the length of the residual byte, of possible end of message without redundancies; - some registers (RPT, SHO, SHC), apt to contain the bit sequence forming the instantaneous state of an outgoing channel, which can be re-written with the results furnished by the operative logic circuit at the rhythm of bit transmission on PCM group; - some means (CV3, CV4) apt to replace in said registers, in synchronism with the outgoing channels, the bit sequence relating to the instantaneous state of the ending channel with the analogous sequence relating to the beginning channel; - some means (SVT, SOT, SCT) apt to store the instantaneous states of non-current channels without requiring any read and write addressing, as they are based on the cyclical shift of the information in synchronism with the incoming PCM group; - some means (MEO, MEC), capable of storing the future octet to be transmitted on each channel and the last command received by the rest of the interface.

Claim 5

Multiple communication interface as in claim 1, characterized in that said fourth plurality of circuits (DSC) comprises: - a memory with a double access path (RAM), which is addressable as a processor memory through one of these paths and as a local memory through the other, which is designed to contain the data arriving at and leaving from the 32 channels of PCM group, and to allow the data transit, from one to the other, without requiring internal transfers, and which contains in addition the work information necessary to the operation of the microprogrammed logic circuit (LMT) of the interface itself; - some circuits of access to said memory (LGA, RAD, LAD), able to always insure the possibility of access without wait at the circuits of said microprogrammed logic circuit, independently of the duration of the reading and writing cycles of the processor; - some means of exchange of service information with the processor (RFM, RFS, RCM, RRC), which can be addressed and accessed by the latter as locations of a peripheral unit and are associated with circuits that allow the dialogue operation with the technique of program interrupt by the interface or with the scanning technique by the processor, such means being organized into registers and FIFO memories to render independent the access times to them by the processor and by the interface logic circuit.

Claim 6

Multiple communication interface as in claim 1, characterized in that said fast microprogrammed logic circuit (LMT) comprises: - a read only memory (RMP), containing microprograms, which can be selected through a manually-operated switch (SWT),' in function of the specific dialogue procedure; - a sequencing logic circuit (SEQ, MJC, MBT, FLG) generating the subsequent microinstruction address in function of commands supplied by the microprogram itself, of codes coming from the processor, of codes contained in the double access path memory (RAM) and of codes coming from said first plurality of circuits (LVI) and from said second plurality of circuits (LVO) through said third plurality of circuits (BTT); - an operative logic arithmetic unit (ALU); - a plurality of operative registers (LUM, ACC, RDA, RCS, RCL).

Claim 7

Multiple communication interface as in claim 1, characterized in that it comprises means (LTT, LTC, TSR, TST) apt to allow the use of channels 0 and 16 in a transparent way, in function of the positioning of a manually-operated switch (COM), executing in both directions a direct transfer from memory location to channel and vice versa without using the algorithms of the procedure on the data they carry.