Data buffer device using first-in first-out memory and data buffer array device

Claim 2

A data buffer device provided with a data line, a read/write control signal line, a strobe signal line, a reset signal line, a chip selection input signal line, a chip selection output signal line and a flag output line, comprising: a first-in first-out memory having an input line and an output line; a latch circuit for latching a chip selection input signal from said chip selection input signal line and outputting the latched signal to said chip selection output signal line as a chip selection output signal; a control circuit initialized by a reset signal from said reset signal line, for controlling said latch circuit at an n-th pulse of every N strobe signal pulses from said strobe signal line, where N and n are predetermined integers and 1>n>N, such that said latch circuit holds said chip selection input signal, and for controlling said latch circuit at every N-th strobe signal pulse such that said latch circuit updates said chip selection output signal; a bus interface circuit connected with said data line and said input line and said output line of said first-in first-out memory and responsive to said chip selection output signal and a read/write control signal from said read/write control signal line, for controlling data transfer between said data line and said first-in first-out memory; and an output circuit, responsive to said read/write control signal, for selecting a lag signal from a plurality of flags outputted from said first-in first-out memory and, responsive to said chip selection input signal, for outputting said flag signal to said flag output line.

Claim 3

A data buffer array apparatus having a data bus line, an external flag line, a block selection input line, an address input line and a read/write control signal line, comprising: a plurality of data buffer devices each having a data line, a flag output line, a chip selection input line, and a chip selection output line, each of said devices for holding a chip selection input signal from said chip selection input line at an n-th access of every N data from said data line, where N and n are redetermined integers and 1>n>N, outputting said chip selection input signal to said chip selection output line as a chip selection output signal during data access from first data to (n-1)th data from said data line where n is greater than 1, outputting said chip selection input signal held in the device to said chip selection output line as a chip selection output signal during data access from n-th data to N-th data from said data line, controlling said flag output line responsive to said chip selection input signal, and controlling data transfer on said data line responsive to said chip selection output signal and a read/write control signal from said read/write control signal line; a decode circuit connected with said chip selection input lines to respective ones of said plurality of data buffer devices, for decoding a block selection signal from said block selection input line and an address signal from said address input line, and for generating chip selection input signals to respective ones of said plurality of data buffer devices; a flag interface circuit connected with said flag output lines from respective ones of said plurality of data buffer devices and responsive to said bock selection signal, for outputting a flag signal to said external flag line; and a bus interface circuit connected with said data lines of respective ones of said plurality of data buffer devices and responsive to a logical ORed signal of said chip selection output signals from respective ones of said plurality of data buffer devices, for controlling data transfer between said data bus line and said respective data lines.

Claim 4

A data buffer array apparatus having a data bus line, an external flag line, a block selection input line, an address input line and a read/write control signal line, comprising: a plurality of data buffer devices each having a data line, a flag output line, a chip selection input line, and a chip selection output line, each of said devices for holding a chip selection input signal from said chip selection input line at an n-th access of every N data from said data line, where N and n are redetermined integers and 1>n>N, outputting said chip selection input signal to said chip selection output line as a chip selection output signal during data access from first data to (n-1)th data from said data line where n is greater than 1, outputting said chip selection input signal held in the device to said chip selection output line as a chip selection output signal during data access from n-th data to N-th data from said data line, controlling said flag output line responsive to said chip selection input signal, and controlling data transfer on said data line responsive to said chip selection output signal and a read/write control signal from said read/write control signal line; a decode circuit connected with said chip selection input lines to respective ones of said plurality of data buffer devices, for decoding a block selection signal from said block selection input line and an address signal from said address input line, and for generating chip selection input signals to respective ones of said plurality of data buffer devices; a flag interface circuit connected with said flag output lines from respective ones of said plurality of data buffer devices and responsive to said bock selection signal, for outputting a flag signal to said external flag line; and a bus interface circuit connected with said data lines of respective ones of said plurality of data buffer devices and responsive to a logical ORed signal of said chip selection output signals from respective ones of said plurality of data buffer devices, for controlling data transfer between said data bus line and said respective data lines.

Claim 5

A data buffer array apparatus of claim 2 wherein each of said data buffer devices further comprises: a first-in first-out memory having an input line and an output line; a latch circuit for latching said chip selection input signal and outputting the latched signal as said chip selection output signal; a control circuit for controlling said latch circuit at said n-th access of every N data, such that said latch circuit holds said chip selection input signal, and for controlling said latch circuit at an N-th access of every N data such that said latch circuit updates said chip selection output signal responsive to said chip selection input signal; a second bus interface circuit connected with said data line and said input line and said output line of said first-in first-out memory and responsive to said chip selection output signal and said read/write control signal, for controlling data transfer between said data line and said first-in first-out memory; and an output circuit, responsive to said read/write signal, for selecting a flag signal out of a plurality of flags outputted from said first-in first-out memory and, responsive to said chip selection input signal, for outputting said flag signal to said flag output line.