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US5056004A
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Program control system which simultaneously executes a program to be repeated and decrements repetition numbers
Assignee: NEC Corp
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Filing: 1988-10-14
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Granted: 1991-10-08
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Expires: 2008-10-14
Abstract
Abstract A for controlling a includes circuit a register for holding the repetition number of a program operation to be repeated, a counter receiving the content of the register and adapted to decrement in response with each execution of the program operation to be repeated, a memory for storing a sequence of instructions, and a controller for receiving an instruction read from the memory modification in a normal condition and to convert the received instruction into a no-operation instruction when the content of the counter becomes a predetermined content.
Inventors
- 👤 Yuko Ohde
- 👤 Hideo Tanaka
- 👤 Ichiro Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/325
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
271 words
A program control circuit comprising: a register for holding a repetition number of a program operation to be repeated, means for modifying content of the register in accordance with each execution of the program operation to be repeated, memory means for storing a sequence of instructions, and means receiving an instruction read from the memory means for transferring the received instruction without modification in a normal condition and for converting the received instruction into a different instruction when the content of the first register is a predetermined content; said modifying means including a counter receiving the content of the register and adapted to change said content in a predetermined counting direction in response to each execution of the operation to be repeatedly executed, the counter generating an output signal when the content of the counter reaches a predetermined value, the transferring and converting means operative in response to the output signal from the counter so as to modify the instruction read from the memory, said memory including an instruction read only memory and the transferring and converting means including a gate array coupled to the read only memory, the gate array being placed in a signal blocking condition in response to the output signal of the counter, and wherein said gate array includes a plurality of two-input gates, each gate having a first input connected to a corresponding bit output of the read only memory, a second input of all the gates being connected to receive the output signal from the counter, and each gate includes a two-input NAND gate and an invertor connected to an output of the NAND gate.
Claim 2
Dependent Claim
271 words
A program control circuit comprising: a register for holding a repetition number of a program operation to be repeated, means for modifying content of the register in accordance with each execution of the program operation to be repeated, memory means for storing a sequence of instructions, and means receiving an instruction read from the memory means for transferring the received instruction without modification in a normal condition and for converting the received instruction into a different instruction when the content of the first register is a predetermined content; said modifying means including a counter receiving the content of the register and adapted to change said content in a predetermined counting direction in response to each execution of the operation to be repeatedly executed, the counter generating an output signal when the content of the counter reaches a predetermined value, the transferring and converting means operative in response to the output signal from the counter so as to modify the instruction read from the memory, said memory including an instruction read only memory and the transferring and converting means including a gate array coupled to the read only memory, the gate array being placed in a signal blocking condition in response to the output signal of the counter, and wherein said gate array includes a plurality of two-input gates, each gate having a first input connected to a corresponding bit output of the read only memory, a second input of all the gates being connected to receive the output signal from the counter, and each gate includes a two-input NAND gate and an invertor connected to an output of the NAND gate.
Claim 3
Dependent Claim
60 words
A circuit as claimed in claim 1 wherein the modifying means includes a counter receiving the content of the register and adapted to be decremented in response to each execution of the operation to be repeatedly executed, the transfer means being in response to a borrow signal from the counter so as to modify the instruction read from the memory.
Claim 4
Dependent Claim
60 words
A circuit as claimed in claim 1 wherein the modifying means includes a counter receiving the content of the register and adapted to be incremented in response to each execution of the operation to be repeatedly executed, the transfer means being in response to a carry signal from the counter so as to modify the instruction read from the memory.
Claim 5
Dependent Claim
262 words
A program control circuit comprising: a counter set with a repetition number of a program operation to be repeated and adapted to modify the content of said counter in response with each execution of the program operation to be repeated, memory means for storing a sequence of instructions, and means receiving an instruction read from the memory means for transferring the received instruction without modification in a normal condition and for converting the received instruction into a different instruction when the content of the first register becomes a predetermined content, said counter adapted to change said content in a predetermined counting direction in response to each execution of the operation to be repeatedly executed, the counter generating an output signal when the content of the counter reaches a predetermined value, the transferring and converting means operative in response to the output signal from the counter so as to modify the instruction read from the memory, said memory includes an instruction read only memory and the transferring and converting means including a gate array coupled to the read only memory, the gate array being placed in a signal blocking condition in response to the output signal of the counter, said gate array including a plurality of two-input gates, each gate having a first input connected to a corresponding bit output of the read only memory and a second input of all the gates being connected to receive the output signal from the counter, and wherein each gate includes a two-input NAND gate and an invertor connected to an output of the NAND gate.
Claim 6
Dependent Claim
262 words
A program control circuit comprising: a counter set with a repetition number of a program operation to be repeated and adapted to modify the content of said counter in response with each execution of the program operation to be repeated, memory means for storing a sequence of instructions, and means receiving an instruction read from the memory means for transferring the received instruction without modification in a normal condition and for converting the received instruction into a different instruction when the content of the first register becomes a predetermined content, said counter adapted to change said content in a predetermined counting direction in response to each execution of the operation to be repeatedly executed, the counter generating an output signal when the content of the counter reaches a predetermined value, the transferring and converting means operative in response to the output signal from the counter so as to modify the instruction read from the memory, said memory includes an instruction read only memory and the transferring and converting means including a gate array coupled to the read only memory, the gate array being placed in a signal blocking condition in response to the output signal of the counter, said gate array including a plurality of two-input gates, each gate having a first input connected to a corresponding bit output of the read only memory and a second input of all the gates being connected to receive the output signal from the counter, and wherein each gate includes a two-input NAND gate and an invertor connected to an output of the NAND gate.
Claim 7
Dependent Claim
50 words
A circuit as claimed in claim 4 wherein the counter is adapted to be decremented in response to each execution of the operation to be repeatedly executed, the transfer means being in response to a borrow signal from the counter so as to modify the instruction read from the memory.
Claim 8
Dependent Claim
50 words
A circuit as claimed in claim 4 wherein the counter is adapted to be incremented in response to each execution of the operation to be repeatedly executed, the transfer means being in response to a carry signal from the counter so as to modifying the instruction read from the memory.
Claim 9
Dependent Claim
63 words
A circuit as claimed in claim 5 wherein the program sequence to be repeatedly executed includes a plurality of instructions and a jump instruction located at the end of the sequence, the program sequence being such that a predetermined instruction located before the jump instruction contains one bit which will generate a signal for decrementing the counter when the predetermined step is executed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |