Microcode control mechanism utilizing programmable microcode repeat counter

Claim 2

In a microprogrammed data processor wherein a sequence of microwords are used to control execution of each processor instruction, an improved microcode control mechanism comprising: instruction circuitry for providing a plural-bit instruction dependent signal indicating the processor instruction to be executed; sequence counter circuitry for supplying a sequence of plural-bit number signals; a programmable logic array mechanism jointly responsive to the instruction dependent signal and to the sequence of number signals for producing a sequence of microwords needed to execute the instruction; repeat circuitry responsive to a predetermined microword for setting the sequence counter circuitry to a count which is less than a current count for causing a selected portion of the microword sequence to be repeated; repeat control circuitry including a repeat counter for counting the number of times the selected portion of the microword sequence is repeated and for disabling the repeat circuitry after a predetermined number of such repeats; and circuitry for loading into the repeat control circuitry a number value which determines the number of repeats that will be allowed for the selected portion of the microword sequence, said number value being variable with each occurrence of an instruction; control circuitry responsive to the microwords from the programmable logic array for producing for each microword a plurality of control point signals for controlling operation of the data processor for one microword cycle; the circuitry for loading the repeat control circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword occurring before occurrence of the selected portion of the microword sequence for loading the repeat counter with an initial count value; the repeat circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword in the selected portion of the microword sequence for supplying a repeat signal to the sequence counter circuitry to a count which initiates the repeating of the selected portion of the microword sequence; repeat control circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword in the selected portion of the microword sequence for changing by a fixed amount the number value in the counter; and the repeat control circuitry includes output circuitry responsive to a predetermined number value in the repeat counter for disabling the supplying of the repeat signal to the sequence counter circuitry.

Claim 3

An improved microcode control mechanism in accordance with claim 1 wherein: the data processor includes a main storage unit for storing a instructions comprising the user program to be performed; the instruction circuitry includes a plural-bit instruction register for receiving from the main storage unit at least an operation code part of the processor instruction to be executed; and the instruction circuitry further includes circuitry coupled to the instruction register for providing the plural-bit instruction dependent signal representing the processor instruction to be executed.

Claim 4

An improved microcode control mechanism in accordance with claim 1 wherein the sequence counter circuitry includes a plural-bit binary counter for supplying the sequence of plural-bit number signals, such number signals being plural-bit binary number signals.

Claim 5

An improved microcode control mechanism in accordance with claim 1 wherein the programmable logic array mechanism includes at least one programmable logic array having an input AND array connected by multiple word lines to an output OR array, with the input AND array being responsive to the instruction dependent signal and to the sequence of number signals for causing the output OR array to produce at least some of the microwords needed to execute the processor instruction.

Claim 6

An improved microcode control mechanism in accordance with claim 1 wherein the programmable logic array mechanism includes: a plurality of programmable logic arrays for individually producing different ones of the microwords needed to execute the processor instruction; and multiplexer circuitry coupled to the outputs of the programmable logic arrays for enabling microwords from different programmable logic arrays to take turns in controlling the operation of the data processor.

Claim 7

An improved microcode control mechanism in accordance with claim 1 wherein: the data processor includes a main storage unit for storing a instructions comprising the user program to be performed; and the circuitry for loading the repeat control circuitry includes circuitry for extracting from the user program in the main storage unit a programmed number value and loading such number value into the repeat control circuitry to establish the number of repeats that will be allowed for the selected portion of the microword sequence.

Claim 8

An improved microcode control mechanism in accordance with claim 1 wherein the circuitry for loading the repeat control circuitry includes circuitry for extracting from a microword occurring before the selected portion of the microword sequence a microprogrammed number value and loading such number value into the repeat control circuitry to establish the number of repeats that will be allowed for the selected portion of the microword sequence.

Claim 9

An improved microcode control mechanism in accordance with claim 1 wherein: the microcode control mechanism includes decoder circuitry responsive to the microwords from the programmable logic array mechanism for producing for each microword a plurality of control point signals for controlling operation of a data processor for one microword cycle; and the repeat circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword in the selected portion of the microword sequence for supplying a reset signal to the sequence counter circuitry for resetting the sequence counter circuitry back to a count which initiates the repeating of the selected portion of the microword sequence.

Claim 10

An improved microcode control mechanism in accordance with claim 1 wherein: the microcode control mechanism includes decoder circuitry responsive to the microwords from the programmable logic array mechanism for producing for each microword a plurality of control point signals for controlling operation of the data processor for one microword cycle; the programmable repeat control circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword in the selected portion of the microword sequence for incrementing the repeat counter; and the programmable repeat control circuitry further includes circuitry responsive to occurrence of a predetermined count in the repeat counter for disabling the repeat circuitry to prevent any further repeat of the selected portion of the microword sequence.

Claim 11

In a microprogrammed data processor wherein a sequence of microwords are used to control execution of each processor instruction, an improved microcode control mechanism comprising: first and second programmable logic array mechanisms responsive to the processor instruction to be executed for respectively producing microwords for first and second segments of the microword sequence needed to execute the instruction; first and second sequence counter mechanisms for respectively driving the first and second programmable logic array mechanisms for enabling them to produce their respective segments of the microword sequence; repeat circuitry responsive to a predetermined microword from the second programmable logic array mechanism for resetting the second sequence counter mechanism for causing a selected portion of the second segment of the microword sequence to be repeated; repeat control circuitry including a repeat counter for counting the number of times the selected portion of the second segment of the microword sequence is repeated and for disabling the repeat circuitry after a predetermined number of such repeats; and circuitry for loading into the repeat control circuitry a number value which determines the number of repeats that will be allowed for the selected portion of the second segment of the microword sequence, said number value being variable with each occurrence of an instruction; control circuitry responsive to the microwords from the programmable logic array mechanism for producing for each microword a plurality of control point signals for controlling operation of the data processor for one microword cycle; the circuitry for loading the repeat control circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword occurring before occurrence of the selected portion of the microword sequence for loading the repeat counter with an initial counter value; the repeat circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword in the selected portion of the microword sequence for supplying a repeat signal to the second sequence counter mechanism for setting the second sequence counter mechanism to a count which initiates the repeating of the selected portion of the microword sequence; the repeat control circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword in the selected portion of the microword sequence for changing by a fixed amount the number value in the counter; and the repeat control circuitry includes output circuitry responsive to a predetermined number value in the repeat counter for disabling the supplying of the repeat signal to the second sequence counter mechanism.

Claim 12

In a microprogrammed data processor wherein a sequence of microwords are used to control execution of each processor instruction, an improved microcode control mechanism comprising: first and second programmable logic array mechanisms responsive to the processor instruction to be executed for respectively producing microwords for first and second segments of the microword sequence needed to execute the instruction; first and second sequence counter mechanisms for respectively driving the first and second programmable logic array mechanisms for enabling them to produce their respective segments of the microword sequence; repeat circuitry responsive to a predetermined microword from the second programmable logic array mechanism for resetting the second sequence counter mechanism for causing a selected portion of the second segment of the microword sequence to be repeated; repeat control circuitry including a repeat counter for counting the number of times the selected portion of the second segment of the microword sequence is repeated and for disabling the repeat circuitry after a predetermined number of such repeats; and circuitry for loading into the repeat control circuitry a number value which determines the number of repeats that will be allowed for the selected portion of the second segment of the microword sequence, said number value being variable with each occurrence of an instruction; control circuitry responsive to the microwords from the programmable logic array mechanism for producing for each microword a plurality of control point signals for controlling operation of the data processor for one microword cycle; the circuitry for loading the repeat control circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword occurring before occurrence of the selected portion of the microword sequence for loading the repeat counter with an initial counter value; the repeat circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword in the selected portion of the microword sequence for supplying a repeat signal to the second sequence counter mechanism for setting the second sequence counter mechanism to a count which initiates the repeating of the selected portion of the microword sequence; the repeat control circuitry includes circuitry responsive to a predetermined control point signal produced by a predetermined microword in the selected portion of the microword sequence for changing by a fixed amount the number value in the counter; and the repeat control circuitry includes output circuitry responsive to a predetermined number value in the repeat counter for disabling the supplying of the repeat signal to the second sequence counter mechanism.

Claim 13

An improved microcode control mechanism in accordance with claim 10 and further including circuitry responsive to a first segment ending microword from the first programmable logic array mechanism for enabling the second programmable logic array mechanism to produce the microwords of the second segment.

Claim 14

An improved microcode control mechanism in accordance with claim 11 wherein: the data processor includes a main storage unit for storing the instructions comprising the user program to be performed; and the circuitry for loading the repeat control circuitry includes circuitry for extracting from the user program in the main storage unit a programmed number value and loading such number value into the repeat control circuitry for establishing the number of repetitions that will be allowed for the selected portion of the second segment of the microword sequence.

Claim 15

An improved microcode control mechanism in accordance with claim 10 wherein the circuitry for loading the repeat control circuitry includes circuitry for extracting from a microword occurring during the first segment of the microword sequence a microprogrammed number value and loading such number value into the repeat control circuitry to establish the number of repeats that will be allowed for the selected portion of the second segment of the microword sequence.