← Back to Patent Explorer
US5055997A Expired / Lapsed US ⏱️ 0.0 years remaining

System with plurality of processing elememts each generates respective instruction based upon portions of individual word received from a crossbar switch

Assignee: US Philips Corp
•
Filing: 1990-10-09
•
Granted: 1991-10-08
•
Expires: 2010-10-09
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A data processor system having at least one arithmetic/logic processor element and at least one memory processor element which can be coupled in circuit using a crossbar switch. The arithmetic/logic processor element is provided with an ALU and a program memory. The ALU has an input for instructions. The instructions can be made up of data from the program memory and data from the crossbar switch via a channel specifically present for the purpose.

Inventors

  • 👤 Robert J. Sluijter
  • 👤 Cornelis M. Huizer
  • 👤 Hendrik Dijkstra

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 22:18
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/267

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 218 words
A data processing system for processing signals presented at an input as a stream of digital data, comprising at least one data processing unit comprising: (a) at least one processor module comprising a plurality of processor elements disposed to function in parallel with one another, said processor elements including at least one processor element chosen from the group consisting of an arithmetic processor element, a logic processor element and a memory processor element; (b) a crossbar switch to which input signals for a first processor module and output signals from processor elements belonging to additional processor modules are supplied and from which input signals for said processor elements belonging to said additional processor modules and output signals from said first processor module are obtained, and from which a plurality of data words are obtained. said arithmetic and logic processor elements each further comprising: (i) a program memory coupled to said crossbar switch; (ii) constructing means coupled to said program memory and said crossbar switch, for obtaining from said crossbar switch, synchronously with said stream of digital data, said data words and for constructing a stream of instructions comprising portions of said data words and portions of words stored in said program memory, and (iii) an arithmetic logic unit having an instruction input for receiving said stream of instructions.
Claim 2
Dependent Claim 218 words
A data processing system for processing signals presented at an input as a stream of digital data, comprising at least one data processing unit comprising: (a) at least one processor module comprising a plurality of processor elements disposed to function in parallel with one another, said processor elements including at least one processor element chosen from the group consisting of an arithmetic processor element, a logic processor element and a memory processor element; (b) a crossbar switch to which input signals for a first processor module and output signals from processor elements belonging to additional processor modules are supplied and from which input signals for said processor elements belonging to said additional processor modules and output signals from said first processor module are obtained, and from which a plurality of data words are obtained. said arithmetic and logic processor elements each further comprising: (i) a program memory coupled to said crossbar switch; (ii) constructing means coupled to said program memory and said crossbar switch, for obtaining from said crossbar switch, synchronously with said stream of digital data, said data words and for constructing a stream of instructions comprising portions of said data words and portions of words stored in said program memory, and (iii) an arithmetic logic unit having an instruction input for receiving said stream of instructions.
Claim 3
Dependent Claim 74 words
A data processor system according to claim 18, wherein a first part of an instruction is formed in said constructing means from a first section of a respective word of a given length stored in the program memory and an equally long data word part which is derived from a data word provided by said crossbar switch, and the remaining part of said instruction is formed by a second section of the respective word.
Claim 4
Dependent Claim 37 words
A data processor system according to claim 2, wherein said constructing means comprises a multiplexer, via which either the first section of said respective word or said data word part forms said first part of said instruction.
Claim 5
Dependent Claim 42 words
A data processor system according to claim 3, wherein the arithmetic and/or logic processor element comprises a shift unit in which data word parts are provided to the constructing means are selected from the data words fed in from the crossbar switch.
Claim 6
Dependent Claim 50 words
A video processor system for processing video signal samples on a real-time basis, provided with a data processor system according to claim 3, in which a clock device for controlling the data processor units has a frequency which has a fixed relationship to the sampling frequency of the video signal.
Claim 7
Dependent Claim 113 words
A data processor system according to claim 2, wherein said constructing means comprises a number of exclusive-OR gates and an equal number of AND gates, each of the bits of the first section of said respective word being fed to a corresponding exclusive-OR gate, while the bits of said data word part are fed to corresponding exclusive-OR gates via respective AND gates controlled from the program memory in a manner such that the output bits, forming the first part of said instruction, from the exclusive-OR gates are either equal to the bits of the first section of the respective word or form a bit-wise combination with the bits from said data word part.
Claim 8
Dependent Claim 42 words
A data processor system according to claim 6, wherein the arithmetic and/or logic processor element comprises a shift unit in which data word parts are provided to the constructing means are selected from the data words fed in from the crossbar switch.
Claim 9
Dependent Claim 50 words
A video processor system for processing video signal samples on a real-time basis, provided with a data processor system according to claim 6, in which a clock device for controlling the data processor units has a frequency which has a fixed relationship to the sampling frequency of the video signal.
Claim 10
Dependent Claim 42 words
A data processor system according to claim 2, wherein the arithmetic and/or logic processor element comprises a shift unit in which data word parts are provided to the constructing means are selected from the data words fed in from the crossbar switch.
Claim 11
Dependent Claim 50 words
A video processor system for processing video signal samples on a real-time basis, provided with a data processor system according to claim 2, in which a clock device for controlling the data processor units has a frequency which has a fixed relationship to the sampling frequency of the video signal.
Claim 12
Dependent Claim 43 words
A data processor system according to claim 1, wherein the arithmetic and/or logic processor element comprises a shift unit in which data word parts are provided to the constructing means which are selected from the data words fed in from the crossbar switch.
Claim 13
Dependent Claim 50 words
A video processor system for processing video signal samples on a real-time basis, provided with a data processor system according to claim 11, in which a clock device for controlling the data processor units has a frequency which has a fixed relationship to the sampling frequency of the video signal.
Claim 14
Dependent Claim 163 words
A data processor system according to claim 1, wherein the arithmetic and/or logic processor element comprises a shift unit in which data word parts are provided to the constructing means which are selected from the data words fed in from the crossbar switch, said shift unit is furthermore controllable from the program memory in a manner such that only logic zeros appear at the output thereof, and in that the constructing means is provided with exclusive-OR gates, each of the bits of the first section of a word stored in the program memory and each of the bits of a data word part is fed to a corresponding exclusive-OR gate, the shift unit being controlled in a manner such that the output bits, forming a first instruction part, from the exclusive-OR gates are either equal to the bits of the first section of a respective word stored in the program memory or a bit-wise combination with the bits of said data word part.
Claim 15
Dependent Claim 50 words
A video processor system for processing video signal samples on a real-time basis, provided with a data processor system according to claim 13, in which a clock device for controlling the data processor units has a frequency which has a fixed relationship to the sampling frequency of the video signal.
Claim 16
Dependent Claim 50 words
A video processor system for processing video signal samples on a real-time basis, provided with a data processor system according to claim 1, in which a clock device for controlling the data processor units has a frequency which has a fixed relationship to the sampling frequency of the video signal.
Claim 17
Dependent Claim 163 words
A data processor system according to claim 2, wherein the arithmetic and/or logic processor element comprises a shift unit in which data word parts are provided to the constructing means which are selected from the data words fed in from the crossbar switch, said shift unit is furthermore controllable from the program memory in a manner such that only logic zeros appear at the output thereof, and in that the constructing means is provided with exclusive-OR gates, each of the bits of the first section of a word stored in the program memory and each of the bits of a data word part is fed to a corresponding exclusive-OR gate, the shift unit being controlled in a manner such that the output bits, forming a first instruction part, from the exclusive-OR gates are either equal to the bits of the first section of the respective word stored in the program memory or a bit-wise combination with the bits of said data word part.

References Cited (Backward Citations)

US3718912A Cited
US3970993A Cited
US4095278A Cited
US4109311A Cited
US4236204A Cited
US4293907A Cited
US4467409A Cited
US4884193A Cited
US4807183A Cited
US4907148A Cited
US4783738A Cited
US4831572A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-10-07 1995-04-08 1995-10-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-10-07 1999-04-08 1999-10-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-10-07 2003-04-08 2003-10-08 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag