US5055418A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating complementary contactless vertical bipolar transistors
Assignee: National Semiconductor Corp
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Filing: 1990-11-13
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Granted: 1991-10-08
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Expires: 2010-11-13
Abstract
Abstract A complementary NPN and PNP contactless vertical transistor structure is formed by a process that includes the steps of providing: (1) a buried layer and P- tub for NPN; (2) a channel stopper for NPN, and a buried layer for PNP; (3) isolation oxide for NPN and PNP; (4) a sink for NPN, and a ground for PNP; (5) a base for NPN, and a sink for PNP; (6) a base for PNP; (7) a N+ poly implant for NPN emitter and PNP extrinsic base; (8) a P+ poly implant for NPN extrinsic base and PNP emitter; (9) poly definition; (10) silicide exclusion for resistors and diodes; (11) contacts; (12) first metal; (13) vias; (14) second metal; and (15) scratch protection.
Inventors
- 👤 Madhukar B. Vora
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:43
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/0119; H10D84/0121; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/67; H10D84/673; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/011
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
176 words
A process for fabricating complementary vertical bipolar transistors on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a first epitaxial layer of an opposite conductivity type on said substrate; introducing into a first region of said first epitaxial layer a fast diffusing dopant of the first conductivity type to form a well, and a slower diffusing dopant of the opposite conductivity type to form a buried layer in said well; introducing into a second region of said first epitaxial layer a dopant of the first conductivity type to form a buried layer; forming a second epitaxial layer on said first epitaxial layer; forming respective epitaxial silicon islands in said second epitaxial layer over said first region and said second region; forming a polysilicon emitter transistor of a first type in the epitaxial silicon island over said first region; and forming a polysilicon emitter transistor of a second type in the isolation island over said second region, said transistor of the second type being complementary to said transistor of the first type.
Claim 2
Dependent Claim
176 words
A process for fabricating complementary vertical bipolar transistors on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a first epitaxial layer of an opposite conductivity type on said substrate; introducing into a first region of said first epitaxial layer a fast diffusing dopant of the first conductivity type to form a well, and a slower diffusing dopant of the opposite conductivity type to form a buried layer in said well; introducing into a second region of said first epitaxial layer a dopant of the first conductivity type to form a buried layer; forming a second epitaxial layer on said first epitaxial layer; forming respective epitaxial silicon islands in said second epitaxial layer over said first region and said second region; forming a polysilicon emitter transistor of a first type in the epitaxial silicon island over said first region; and forming a polysilicon emitter transistor of a second type in the isolation island over said second region, said transistor of the second type being complementary to said transistor of the first type.
Claim 3
Dependent Claim
19 words
A process as in claim 1, further comprising the step of doping said substrate to achieve a low resistivity.
Claim 4
Dependent Claim
39 words
A process as in claim 2 wherein said fast diffusing dopant is aluminum, further comprising the step of achieving a p-well having a substantially uniform aluminum concentration of 2×10 15 aluminum atoms/cm 3 and electrically integrated with said substrate.
Claim 5
Dependent Claim
21 words
A process as in claim 3, further comprising the step of doping said substrate to achieve a resistivity of 0.001 ohm-centimeter.
Claim 6
Dependent Claim
32 words
A process as in claim 1, wherein said first conductivity type is p-type, said opposite conductivity type is n-type, said first transistor type is NPN, and said second transistor type is PNP.
Claim 7
Dependent Claim
135 words
A process for fabricating complementary vertical bipolar transistors on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a first epitaxial silicon island underlaid by a buried layer of an opposite conductivity type in a well of the first conductivity type within an epitaxial silicon layer upon said substrate, said well being electrically integrated with said substrate; forming a polysilicon emitter transistor of a first type in said first epitaxial silicon island; forming a second epitaxial silicon island underlaid by a buried layer of the first conductivity type in a region of said epitaxial silicon layer of the opposite conductivity type; and forming a polysilicon emitter transistor of a second type in said second isolation island, said transistor of the second type being complementary to said transistor of the first type.
Claim 8
Dependent Claim
135 words
A process for fabricating complementary vertical bipolar transistors on a semiconductor substrate of a first conductivity type, comprising the steps of: forming a first epitaxial silicon island underlaid by a buried layer of an opposite conductivity type in a well of the first conductivity type within an epitaxial silicon layer upon said substrate, said well being electrically integrated with said substrate; forming a polysilicon emitter transistor of a first type in said first epitaxial silicon island; forming a second epitaxial silicon island underlaid by a buried layer of the first conductivity type in a region of said epitaxial silicon layer of the opposite conductivity type; and forming a polysilicon emitter transistor of a second type in said second isolation island, said transistor of the second type being complementary to said transistor of the first type.
Claim 9
Dependent Claim
12 words
A process as in claim 6, wherein said substrate is low resistivity.
Claim 10
Dependent Claim
24 words
A process as in claim 7, wherein said well is a p-well having a substantially uniform aluminum concentration of 2×10 15 atoms/cm 3 .
Claim 11
Dependent Claim
15 words
A process as in claim 8, wherein the resistivity of said substrate is 0.001 ohm-centimeter.
Claim 12
Dependent Claim
32 words
A process as in claim 6, wherein said first conductivity type is p-type, said opposite conductivity type is n-type, said first transistor type is NPN, and said second transistor type is PNP.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
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